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Data Sheet, Rev. 2 October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Features
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1394a-2000 OHCI link and PHY core function in single device: -- Enables smaller, simpler, more efficient motherboard and add-in card designs by replacing two components with one -- Enables lower system costs -- Leverages proven 1394a-2000 PHY core design -- Demonstrated compatibility with current Microsoft Windows (R) drivers and common applications -- Demonstrated interoperability with existing, as well as older, 1394 consumer electronics and peripherals products -- Feature-rich implementation for high performance in common applications -- Supports low-power system designs (CMOS implementation, power management features) -- Provides LPS, LKON, and CNA outputs to support legacy power management implementations OHCI: -- Complies with OHCI 1.1 WHQL requirements -- Complies with Microsoft Windows Logo Program System and Device Requirements -- Listed on Windows Hardware Compatibility List
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http://www.microsoft.com/hcl/results.asp
-- Compatible with Microsoft Windows and MacOS (R) operating systems -- 4 Kbyte isochronous transmit FIFO -- 2 Kbyte asynchronous transmit FIFO -- 4 Kbyte isochronous receive FIFO -- 2 Kbyte asychronous receive FIFO -- Dedicated asynchronous and isochronous descriptor-based DMA engines -- Eight isochronous transmit contexts -- Eight isochronous receive contexts -- Prefetches isochronous transmit data -- Supports posted write transactions
1394a-2000 PHY core: -- Compliant with IEEE (R) 1394a-2000, Standard for a High Performance Serial Bus (Supplement) -- Provides three fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic -- Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders -- While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port -- Does not require external filter capacitor for PLL -- Supports PHY core-link interface initialization and reset -- Supports link-on as a part of the internal PHY core-link interface -- 25 MHz crystal oscillator and internal PLL provide transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s, and internal link-layer controller clock at 50 MHz -- Interoperable across 1394 cable with 1394 physical layers (PHY core) using 5 V supplies -- Node power-class information signaling for system power management -- Supports ack-accelerated arbitration and fly-by concatenation -- Supports arbitrated short bus reset to improve utilization of the bus -- Fully supports suspend/resume -- Supports connection debounce -- Supports multispeed packet concatenation -- Supports PHY pinging and remote PHY access packets -- Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V -- Separate cable bias and driver termination voltage supply for each port Link: -- Cycle master and isochronous resource manager capable -- Supports 1394a-2000 acceleration features
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Table of Contents
Contents Page
Features ...................................................................................................................................................................1 FW323 Functional Overview ....................................................................................................................................7 Other Features ......................................................................................................................................................... 7 FW323 Functional Description ........................................................................................................................... 7 PCI Core ............................................................................................................................................................7 Isochronous Data Transfer ................................................................................................................................ 8 Asynchronous Data Transfer .............................................................................................................................8 Asynchronous Register ...................................................................................................................................... 8 Serial EEPROM Interface ..................................................................................................................................9 Link Core ............................................................................................................................................................9 PHY Core ........................................................................................................................................................... 9 Pin Information ....................................................................................................................................................... 13 Application Schematic ............................................................................................................................................ 18 Internal Registers ...................................................................................................................................................20 PCI Configuration Registers ............................................................................................................................ 20 Vendor ID Register .......................................................................................................................................... 21 Device ID Register ........................................................................................................................................... 22 PCI Command Register ................................................................................................................................... 23 PCI Status Register ......................................................................................................................................... 25 Class Code and Revision ID Register .............................................................................................................. 26 Latency Timer and Class Cache Line Size Register ........................................................................................ 27 Header Type and BIST Register ......................................................................................................................28 OHCI Base Address Register .......................................................................................................................... 30 PCI Subsystem Identification Register ............................................................................................................. 32 PCI Power Management Capabilities Pointer Register .................................................................................... 32 Interrupt Line and Pin Register ........................................................................................................................ 33 MIN_GNT and MAX_LAT Register .................................................................................................................. 34 PCI OHCI Control Register .............................................................................................................................. 35 Capability ID and Next Item Pointer Register .................................................................................................. 37 Power Management Capabilities Register ....................................................................................................... 38 Power Management Control and Status Register ............................................................................................40 Power Management Extension Register .......................................................................................................... 42 OHCI Registers ................................................................................................................................................ 43 OHCI Version Register .................................................................................................................................... 46 GUID ROM Register ........................................................................................................................................ 48 Asynchronous Transmit Retries Register ......................................................................................................... 50 CSR Data Register .......................................................................................................................................... 52 CSR Compare Register ................................................................................................................................... 54 CSR Control Register ...................................................................................................................................... 56 Configuration ROM Header Register ...............................................................................................................58 Bus Identification Register ............................................................................................................................... 60 Bus Options Register .......................................................................................................................................62 GUID High Register ......................................................................................................................................... 64 GUID Low Register .......................................................................................................................................... 66 Configuration ROM Mapping Register ............................................................................................................. 68 Posted Write Address Low Register ................................................................................................................ 70 Posted Write Address High Register ...............................................................................................................72 Vendor ID Register .......................................................................................................................................... 74 Host Controller Control Register ......................................................................................................................76 Self-ID Count Register ..................................................................................................................................... 80 Isochronous Receive Channel Mask High Register ......................................................................................... 82 2 Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Table of Contents (continued)
Contents Page
Isochronous Receive Channel Mask Low Register .......................................................................................... 84 Interrupt Event Register ................................................................................................................................... 86 Interrupt Mask Register .................................................................................................................................... 89 Isochronous Transmit Interrupt Event Register ................................................................................................ 91 Isochronous Transmit Interrupt Mask Register ................................................................................................ 93 Isochronous Receive Interrupt Event Register ................................................................................................. 94 Isochronous Receive Interrupt Mask Register ................................................................................................. 96 Fairness Control Register ................................................................................................................................ 97 Link Control Register ........................................................................................................................................99 Node Identification Register ........................................................................................................................... 101 PHY Core Layer Control Register .................................................................................................................. 103 Isochronous Cycle Timer Register ................................................................................................................. 105 Asynchronous Request Filter High Register .................................................................................................. 107 Asynchronous Request Filter Low Register ................................................................................................... 110 Physical Request Filter High Register ............................................................................................................113 Physical Request Filter Low Register ............................................................................................................116 Asynchronous Context Control Register ........................................................................................................ 119 Asynchronous Context Command Pointer Register ....................................................................................... 121 Isochronous Transmit Context Control Register ............................................................................................ 123 Isochronous Transmit Context Command Pointer Register ........................................................................... 125 Isochronous Receive Context Control Register ............................................................................................. 127 Isochronous Receive Context Command Pointer Register ............................................................................ 129 Isochronous Receive Context Match Register ............................................................................................... 131 FW323 Vendor Specific Registers ................................................................................................................. 133 Isochronous DMA Control .............................................................................................................................. 134 Asynchronous DMA Control ........................................................................................................................... 135 Link Options ................................................................................................................................................... 136 Crystal Selection Considerations ..........................................................................................................................138 Load Capacitance .......................................................................................................................................... 138 Board Layout ..................................................................................................................................................138 Absolute Maximum Ratings .................................................................................................................................. 138 Electrical Characteristics ......................................................................................................................................139 Timing Characteristics .......................................................................................................................................... 141 ac Characteristics of Serial EEPROM Interface Signals ...................................................................................... 141 Internal Register Configuration ............................................................................................................................. 144 PHY Core Register Map for Cable Environment ............................................................................................ 144 PHY Core Register Fields for Cable Environment .........................................................................................145 Outline Diagrams ..................................................................................................................................................150 128-Pin TQFP ................................................................................................................................................ 150
Figure
Page
Figure 1. FW323 Functional Block Diagram .............................................................................................................7 Figure 2. PHY Core Block Diagram ........................................................................................................................ 12 Figure 3. Pin Assignments for FW323 .................................................................................................................... 13 Figure 4. Application Schematic for FW323 ........................................................................................................... 19 Figure 5. Bus Timing ............................................................................................................................................ 142 Figure 6. Write Cycle Timing ................................................................................................................................ 142 Figure 7. Data Validity .......................................................................................................................................... 142 Figure 8. Start and Stop Definition ....................................................................................................................... 143 Figure 9. Output Acknowledge ............................................................................................................................. 143 Agere Systems Inc. 3
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Table of Contents (continued)
Table Page
Table 1. Pin Descriptions ........................................................................................................................................14 Table 2. Bit-Field Access Tag Description ..............................................................................................................20 Table 3. PCI Configuration Register Map ...............................................................................................................20 Table 4. Vendor ID Register ...................................................................................................................................21 Table 5. Device ID Register ....................................................................................................................................22 Table 6. PCI Command Register ............................................................................................................................23 Table 7. PCI Command Register Description .........................................................................................................24 Table 8. PCI Status Register ..................................................................................................................................25 Table 9. Class Code and Revision ID Register .....................................................................................................26 Table 10. Class Code and Revision ID Register Description .................................................................................27 Table 11. Latency Timer and Class Cache Line Size Register ..............................................................................27 Table 12. Latency Timer and Class Cache Line Size Register Description ..........................................................28 Table 13. Header Type and BIST Register ............................................................................................................28 Table 14. Header Type and BIST Register Description .........................................................................................29 Table 15. OHCI Base Address Register .................................................................................................................30 Table 16. OHCI Base Address Register Description ..............................................................................................31 Table 17. PCI Subsystem Identification Register Description ................................................................................32 Table 18. PCI Power Management Capabilities Pointer Register ..........................................................................32 Table 19. Interrupt Line and Pin Register ...............................................................................................................33 Table 20. Interrupt Line and Pin Register Description ............................................................................................33 Table 21. MIN_GNT and MAX_LAT Register .........................................................................................................34 Table 22. MIN_GNT and MAX_LAT Register Description ......................................................................................34 Table 23. PCI OHCI Control Register ....................................................................................................................35 Table 24. PCI OHCI Control Register Description ..................................................................................................36 Table 25. Capability ID and Next Item Pointer Register .........................................................................................37 Table 26. Capability ID and Next Item Pointer Register Description ......................................................................37 Table 27. Power Management Capabilities Register .............................................................................................38 Table 28. Power Management Capabilities Register Description ..........................................................................39 Table 29. Power Management Control and Status Register .................................................................................40 Table 30. Power Management Control and Status Register Description ...............................................................41 Table 31. Power Management Extension Register ................................................................................................42 Table 32. Power Management Extension Register Description ............................................................................42 Table 33. OHCI Register Map ................................................................................................................................43 Table 34. OHCI Version Register ...........................................................................................................................46 Table 35. OHCI Version Register Description ........................................................................................................47 Table 36. GUID ROM Register ..............................................................................................................................48 Table 37. GUID ROM Register Description ............................................................................................................49 Table 38. Asynchronous Transmit Retries Register ..............................................................................................50 Table 39. Asynchronous Transmit Retries Register Description ............................................................................51 Table 40. CSR Data Register .................................................................................................................................52 Table 41. CSR Data Register Description ..............................................................................................................53 Table 42. CSR Compare Register ..........................................................................................................................54 Table 43. CSR Compare Register Description .......................................................................................................55 Table 44. CSR Control Register .............................................................................................................................56 Table 45. CSR Control Register Description .........................................................................................................57 Table 46. Configuration ROM Header Register ......................................................................................................58 Table 47. Configuration ROM Header Register Description ..................................................................................59 Table 48. Bus Identification Register ......................................................................................................................60 Table 49. Bus Identification Register Description ...................................................................................................61 Table 50. Bus Options Register ..............................................................................................................................62 Table 51. Bus Options Register Description ...........................................................................................................63 4 Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Table of Contents (continued)
Table Page
Table 52. GUID High Register ................................................................................................................................64 Table 53. GUID High Register Description .............................................................................................................65 Table 54. GUID Low Register .................................................................................................................................66 Table 55. GUID Low Register Description ..............................................................................................................67 Table 56. Configuration ROM Mapping Register ....................................................................................................68 Table 57. Configuration ROM Mapping Register Description .................................................................................69 Table 58. Posted Write Address Low Register .......................................................................................................70 Table 59. Posted Write Address Low Register Description ....................................................................................71 Table 60. Posted Write Address High Register ......................................................................................................72 Table 61. Posted Write Address High Register Description ...................................................................................73 Table 62. Vendor ID Register .................................................................................................................................74 Table 63. Vendor ID Register Description ..............................................................................................................75 Table 64. Host Controller Control Register .............................................................................................................76 Table 65. Host Controller Control Register Description ..........................................................................................77 Table 66. Self-ID Buffer Pointer Register ...............................................................................................................78 Table 67. Self-ID Buffer Pointer Register Description ............................................................................................79 Table 68. Self-ID Count Register ............................................................................................................................80 Table 69. Self-ID Count Register Description .........................................................................................................81 Table 70. Isochronous Receive Channel Mask High Register ...............................................................................82 Table 71. Isochronous Receive Channel Mask High Register Description ............................................................83 Table 72. Isochronous Receive Channel Mask Low Register ................................................................................84 Table 73. Isochronous Receive Channel Mask Low Register Description ............................................................85 Table 74. Interrupt Event Register ..........................................................................................................................86 Table 75. Interrupt Event Register Description .......................................................................................................87 Table 76. Interrupt Mask Register ..........................................................................................................................89 Table 77. Interrupt Mask Register Description .......................................................................................................90 Table 78. Isochronous Transmit Interrupt Event Register ......................................................................................91 Table 79. Isochronous Transmit Interrupt Event Register Description ...................................................................92 Table 80. Isochronous Transmit Interrupt Mask Register .......................................................................................93 Table 81. Isochronous Receive Interrupt Event Register .......................................................................................94 Table 82. Isochronous Receive Interrupt Event Description ..................................................................................95 Table 83. Isochronous Receive Interrupt Mask Register ........................................................................................96 Table 84. Fairness Control Register .......................................................................................................................97 Table 85. Fairness Control Register Description ....................................................................................................98 Table 86. Link Control Register .............................................................................................................................99 Table 87. Link Control Register Description ........................................................................................................100 Table 88. Node Identification Register .................................................................................................................101 Table 89. Node Identification Register Description ..............................................................................................102 Table 90. PHY Core Layer Control Register ........................................................................................................103 Table 91. PHY Core Layer Control Register Description .....................................................................................104 Table 92. Isochronous Cycle Timer Register .......................................................................................................105 Table 93. Isochronous Cycle Timer Register Description ....................................................................................106 Table 94. Asychronous Request Filter High Register ..........................................................................................107 Table 95. Asynchronous Request Filter High Register Description ......................................................................108 Table 96. Asynchronous Request Filter Low Register ........................................................................................110 Table 97. Asynchronous Request Filter Low Register Description ......................................................................111 Table 98. Physical Request Filter High Register ..................................................................................................113 Table 99. Physical Request Filter High Register Description ...............................................................................114 Table 100. Physical Request Filter Low Register ................................................................................................116 Table 101. Physical Request Filter Low Register Description ..............................................................................117 Table 102. Asynchronous Context Control Register ............................................................................................119 Agere Systems Inc. 5
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Table of Contents (continued)
Table Page
Table 103. Asynchronous Context Control Register Description ........................................................................120 Table 104. Asynchronous Context Command Pointer Register ..........................................................................121 Table 105. Asynchronous Context Command Pointer Register Description ........................................................122 Table 106. Isochronous Transmit Context Control Register .................................................................................123 Table 107. Isochronous Transmit Context Control Register Description .............................................................124 Table 108. Isochronous Transmit Context Command Pointer Register ...............................................................125 Table 109. Isochronous Transmit Context Command Pointer Register Description ............................................126 Table 110. Isochronous Receive Context Control Register ..................................................................................127 Table 111. Isochronous Receive Context Control Register Description ...............................................................128 Table 112. Isochronous Receive Context Command Pointer Register ................................................................129 Table 113. Isochronous Receive Context Command Pointer Register Description .............................................130 Table 114. Isochronous Receive Context Match Register ...................................................................................131 Table 115. Isochronous Receive Context Match Register Description ................................................................132 Table 116. FW323 Vendor Specific Registers Description ...................................................................................133 Table 117. Isochronous DMA Control Registers Description ...............................................................................134 Table 118. Asynchronous DMA Control Registers Description ............................................................................135 Table 119. Link Registers Description ..................................................................................................................136 Table 120. ROM Format Description ....................................................................................................................137 Table 121. Absolute Maximum Ratings ................................................................................................................138 Table 122. Analog Characteristics ........................................................................................................................139 Table 123. Driver Characteristics .........................................................................................................................140 Table 124. Device Characteristics ........................................................................................................................140 Table 125. Switching Characteristics ...................................................................................................................141 Table 126. Clock Characteristics ..........................................................................................................................141 Table 127. ac Characteristics of Serial EEPROM Interface Signals ....................................................................141 Table 128. PHY Core Register Map for the Cable Environment ..........................................................................144 Table 129. PHY Core Register Fields for Cable Environment ..............................................................................145 Table 130. PHY Core Register Page 0: Port Status Page ...................................................................................147 Table 131. PHY Core Register Port Status Page Fields .....................................................................................148 Table 132. PHY Core Register Page 1: Vendor Identification Page ....................................................................149 Table 133. PHY Core Register Vendor Identification Page Fields .......................................................................149
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Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
FW323 Functional Overview
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PCI: -- Revision 2.2 compliant -- 33 MHz/32-bit operation -- Programmable burst size for PCI data transfer -- Supports PCI Bus Power Management Interface Specification v.1.1 -- Supports clockrun protocol per PCI Mobile Design Guide -- Global byte swap function
Other Features
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I2C serial ROM interface CMOS process 3.3 V operation, 5 V tolerant inputs 128-pin TQFP package
The FW323 is the Agere Systems Inc. implementation of a high-performance, PCI bus-based open host controller for implementation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and costeffective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized.
OHCI ASYNC CABLE PORT 2 PCI BUS PCI CORE LINK CORE PHY CORE CABLE PORT 1 CABLE PORT 0
ROM I/F
OHCI ISOCH
5-6250 (F).e
Figure 1. FW323 Functional Block Diagram
FW323 Functional Description
The FW323 is comprised of five major functional sections (see Figure 1): PCI core, isochronous data transfer, asynchronous data transfer, link core, and PHY core. The following is a general description of each of the five major sections.
to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory. The PCI core also supports the PCI Bus Power Management Interface Specification v.1.1. Included in this support is a standard power management register interface accessible through the PCI configuration space. Through this register interface, software is able to transition the FW323 into four distinct power consumption states (D0, D1, D2, and D3). This permits software to selectively increase/decrease the power consumption of the FW323 for reasons such as periods of system inactivity or power conservation. In addition, the FW323 also includes support for hardware wake-up mechanisms through power management events 7
PCI Core
The PCI core serves as the interface to the PCI bus. It contains the state machines that allow the FW323 to respond properly when it is the target of the transaction. During 1394 packet transmission or reception, the PCI core arbitrates for the PCI bus and enables the FW323 Agere Systems Inc.
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
FW323 Functional Description (continued)
(PMEs). When the FW323 is in a low-power state, PMEs provide a hardware mechanism for requesting a software wake-up. Together, the power management register interface and PME support within the FW323 combine to form an efficient means for implementing power management.
1. Fetch a descriptor block from host memory. 2. Fetch data specified by the descriptor block from host memory and place it into the isochronous transmit FIFO. 3. Data in FIFO is read by the link and sent to the PHY core device interface. Isochronous Receive DMA (IRDMA) The isochronous receive DMA module moves data from the receive FIFO to host memory. It consists of isochronous contexts, each of which is independently controlled by software. Normally, each context can process data on a single 1394 isochronous channel. However, software can select one context to receive data on multiple channels. When IRDMA detects that the link core has placed data into the receive FIFO, it immediately reads out the first word in the FIFO, which makes up the header of the isochronous packet. IRDMA extracts the channel number for the packet and packet filtering controls from the header. This information is compared with the control registers for each context to determine if any context is to process this packet. If a match is found, IRDMA will request access to the PCI bus. When granted PCI access, a descriptor block is fetched from host memory. The descriptor provides information about the host memory block allocated for the incoming packet. IRDMA then reads the packet from the receive FIFO and writes the data to host memory via the PCI bus. If no match is found, IRDMA will read the remainder of the packet from the receive FIFO, but not process the data in any way.
Isochronous Data Transfer
The isochronous data transfer logic handles the transfer of isochronous data between the link core and the PCI interface module. It consists of the isochronous register module, the isochronous transmit DMA module, the isochronous receive DMA module, the isochronous transmit FIFO, and the isochronous receive FIFO. Isochronous Register The isochronous register module operates on PCI slave accesses to OHCI registers within the isochronous block. The module also maintains the status of interrupts generated within the isochronous block and sends the isochronous interrupt status to the OHCI interrupt handler block. Isochronous Transmit DMA (ITDMA) The isochronous transmit DMA module moves data from host memory to the link core, which will then send the data to the 1394 bus. It consists of isochronous contexts, each of which is independently controlled by software, and can send data on a 1394 isochronous channel. During each 1394 isochronous cycle, the ITDMA module will service each of the contexts and attempt to process one 1394 packet for each context. If a context is active, ITDMA will request access to the PCI bus. When granted PCI access, a descriptor block is fetched from host memory. This data is decoded by ITDMA to determine how much data is required and where in host memory the data resides. ITDMA initiates another PCI access to fetch this data, which is placed into the transmit FIFO for processing by the link core. If the context is not active, it is skipped by ITDMA for the current cycle. After processing each context, ITDMA writes a cycle marker word in the transmit FIFO to indicate to the link core that there is no more data for this isochronous cycle. As a summary, the major steps for the FW323 ITDMA to transmit a packet are the following:
Asynchronous Data Transfer
The ASYNC block is functionally partitioned into two independent logic blocks for transmitting and receiving 1394 packets. The ASYNC_TX unit is responsible for packet transmission while the ASYNC_RX unit processes received data.
Asynchronous Register
The asynchronous register module operates on PCI slave accesses to OHCI registers within the asynchronous block. The module also maintains the status of interrupts generated within the asynchronous block and sends the asynchronous interrupt status to the OHCI interrupt handler block. Agere Systems Inc.
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
ROM_CLK is an output clock provided by the FW323 to the external EEPROM. ROM_AD is bidirectional and is used for serial data/control transfer between the FW323 and the external EEPROM. The FW323 uses this interface to read the contents of the serial EEPROM during initial power-up or when a hardware reset occurs. The FW323 also makes the serial ROM interface visible to software through the OHCI defined GUID ROM register. When the FW323 is operational, the GUID ROM register allows software to initiate reads to the external EEPROM.
FW323 Functional Description (continued)
Asynchronous Transmit (ASYNC_TX) The ASYNC_TX block of the FW323 manages the asynchronous transmission of either request or response packets. The mechanism for asynchronous transmission of requests and responses are similar. The only difference is the system memory location of the buffer descriptor list when processing the two contexts. Therefore, the discussion below, which is for asynchronous transmit requests, parallels that of the asynchronous transmit response. The FW323 asynchronous transmission of packets involves the following steps: 1. Fetch complete buffer descriptor block from host memory. 2. Get data from system memory and store into async FIFO. 3. Request transfer of data from FIFO to link device. 4. Handle retries, if any. 5. Handle errors in steps 1 to 4. 6. End the transfer if there are no errors. Asynchronous Receive (ASYNC_RX) The ASYNC_RX block of the FW323 manages the processing of received packets. Data packets are parsed and stored in a dedicated asynchronous receive FIFO. Command descriptors are read through the PCI interface to determine the disposition of the data arriving through the 1394 link. The header of the received packet is processed to determine, among other things, the following: 1. The type of packet received. 2. The source and destinations. 3. The data and size, if any. 4. The operation required, if any. For example, compare and swap operation. The ASYNC block also handles DMA transfers of selfID packets during the 1394 bus initialization phase and block transactions associated with physical request.
Link Core
It is the responsibility of the link to ascertain if a received packet is to be forwarded to the OHCI for processing. If so, the packet is directed to a proper inbound FIFO for either the isochronous block or the asynchronous block to process. The link is also responsible for CRC generation on outgoing packets and CRC checking on receiving packets. To become aware of data to be sent outbound on 1394 bus, the link must monitor the OHCI FIFOs looking for packets in need of transmission. Based on data received from the OHCI block, the link will form packet headers for the 1394 bus. The link will alert the PHY core as to the availability of the outbound data. It is the link's function to generate CRC for the outbound data. The link also provides PHY core register access for the OHCI.
PHY Core
The PHY core provides the analog physical layer functions needed to implement a three-port node in a cable-based IEEE 1394-1995 and IEEE 1394a-2000 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PHY core interfaces with the link core. The PHY core requires either an external 24.576 MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 400 MHz reference signal. The 400 MHz reference signal is internally divided to provide the 49.152 MHz, 98.304 MHz, and 196.608 MHz clock signals that control transmission of the outbound clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. 9
Serial EEPROM Interface
The FW323 features an I2C compliant serial ROM interface that allows for the connection of an external serial EEPROM. The interface provides a mechanism to store configuable data such as the global unique identification (GUID) within an external EEPROM. The interface consists of the ROM_AD and ROM_CLK pins. Agere Systems Inc.
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
FW323 Functional Description (continued)
The PHY/link interface is a direct connection and does not provide isolation. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPA and TPB cable pair(s). During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA and TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two, four, or eight parallel streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. This monitor is called bias-detect. The TPBIAS circuit monitors the value of incoming TPA pair common-mode voltage when local TPBIAS is inactive. Because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. The monitor is called connect-detect. Both the TPB bias-detect monitor and TPBIAS connect-detect monitor are used in suspend/resume signaling and cable connection detection. The PHY core provides a 1.86 V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 V or 3 V nominal supplies. This bias voltage source should be 10
stabilized by using an external filter capacitor of approximately 0.33 F. The port transmitter circuitry and the receiver circuitry are disabled when the port is disabled, suspended, or disconnected. The line drivers in the PHY core operate in a highimpedance current mode and are designed to work with external 112 line-termination resistor networks. One network is provided at each end of each twisted pair cable. Each network is composed of a pair of series-connected 56 resistors. The midpoint of the pair of resistors that is directly connected to the twisted pair A (TPA) signals is connected to the TPBIAS voltage signal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB) signals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 k and 220 pF, respectively. The value of the external resistors are specified to meet the draft standard specifications when connected in parallel with the internal receiver circuits. The driver output current, along with other internal operating currents, is set by an external resistor. This resistor is connected between the R0 and R1 signals and has a value of 2.49 k 1%. Four signals are used as inputs to set four configuration status bits in the self-identification (selfID) packet. These signals are hardwired high or low as a function of the equipment design. PC[0:2] are the three signals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth signal (CONTENDER), as an input, indicates whether a node is a contender for bus manager. When the CONTENDER signal is asserted, it means the node is a contender for bus manager. When the signal is not asserted, it means that the node is not a contender. The contender bit corresponds to bit 20 in the self-ID packet, PC0 corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23 (see Table 4-29 of the IEEE 1394-1995 standard for additional details). When the power supply of the PHY core is removed while the twisted-pair cables are connected, the PHY core transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the TPBIAS signal voltage on the other end of the cable. For reliable operation, the TPB signals must be terminated using the normal termination network,
Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
The internal link power status (LPS) signal works with the internal LinkOn signal to manage the LLC power usage of the node. The LPS signal indicates that the LLC of the node is powered up or down. If LPS is inactive for more than 1.2 s and less than 25 s, the internal PHY/link interface is reset. If LPS is inactive for greater than 25 s, the PHY will disable the internal PHY/link interface to save power. The FW323 continues its repeater function. If the PHY then receives a link-on packet, the internal LinkOn signal is activated to output a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the internal LPS signal communicates this to the PHY and the internal PHY/link interface is enabled. Internal LinkOn signal is turned off when LCtrl bit is set. Three of the signals are used to set up various test conditions used in manufacturing. These signals (SE, SM, and PTEST) should be connected to VSS for normal operation.
FW323 Functional Description (continued)
regardless of whether a cable is connected to port or not connected to a port. For those applications, when FW323 is used with one or more of the ports not brought out to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. Note: All gap counts on all nodes of a 1394 bus must be identical. This may be accomplished by using PHY core configuration packets (see Section 4.3.4.3 of IEEE 1394-1995 standard) or by using two bus resets, which resets the gap counts to the maximum level (3Fh).
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
FW323 Functional Description (continued)
CPS LPS SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 LINKON PC0 PC1 PC2 CONTENDER SE SM LINK INTERFACE I/O
RECEIVED DATA DECODER/ RETIMER
BIAS VOLTAGE AND CURRENT GENERATOR
R0 R1
TPA0+ TPA0- ARBITRATION AND CONTROL STATE MACHINE LOGIC
TPBIAS0
CABLE PORT 0 TPB0+ TPB0-
RESETN
TRANSMIT DATA ENCODER
CABLE PORT 1
TPA1+ TPA1- TPBIAS1 TPB1+ TPB1- TPA2+ TPA2- TPBIAS2 TPB2+ TPB2-
CABLE PORT 2
CRYSTAL OSCILLATOR, PLL SYSTEM, AND CLOCK GENERATOR
XI XO
5-5459.i(F) R.01
Figure 2. The PHY Core Block Diagram
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Pin Information
NC NC SE SM PTEST RESETN XO XI PLLVSS PLLVDD R1 R0 VDDA VSSA TPBIAS0 TPA0+ TPA0- TPB0+ TPB0- TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- VDDA VSSA 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VDD VSS CARDBUSN NC CNA NANDTREE TEST1 ROM_CLK ROM_AD TEST0 VDD VSS CLKRUNN PCI_INTAN PCI_RSTN PCI_GNTN PCI_REQN PCI_PMEN VDD PCI_CLK VSS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD VSS PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] VSS PCI_CBEN[3] PCI_IDSEL PCI_AD[23] PCI_AD[22] VDD VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSSA TPBIAS2 TPA2+ TPA2- TPB2+ TPB2- VDDA VSSA CPS VDD NC LPS LKON PC0 PC1 PC2 CONTENDER PCI_VIOS PCI_AD[0] PCI_AD[1] VDD VSS PCI_AD[2] PCI_AD[3] PCI_AD[4] VSS PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_CBEN[0] VDD VSS PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] VSS PCI_AD[12]
PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] VDD VSS PCI_AD[17] PCI_AD[16] PCI_CBEN[2] PCI_FRAMEN VDD VSS PCI_IRDYN PCI_TRDYN PCI_DEVSELN PCI_STOPN VDD VSS PCI_PERRN PCI_SERRN PCI_PAR PCI_CBEN[1] VSS PCI_AD[15] PCI_AD[14] PCI_AD[13]
5-7838 (F)a
Note: Active-low signals within this document are indicated by an N following the symbol names.
Figure 3. Pin Assignments for the FW323
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Pin Information (continued)
Table 1. Pin Descriptions Pin 1 2 3 Symbol* VDD VSS CARDBUSN Type -- -- I Description Power. Ground. CardBusN (Active-Low). Selects mode of operation for PCI output buffers. Tie low for cardbus operation, high for PCI operation. An internal pull-up is provided to force buffers to PCI mode, if no connection is made to this pin. No Connect. Cable Not Active. CNA output is provided for use in legacy power management systems. Nand Tree Test Output. When the chip is placed into the NAND tree test mode, the pin is the output of the NAND tree logic. This pin is not used during functional operation. Test. Used for device testing. Tie to VSS. ROM Clock. ROM Address/Data. Test. Used for device testing. Tie to VSS. Power. Ground. CLKRUNN (Active-Low). Optional signal for PCI mobile environment. If not used, CLKRUNN pin needs to be pulled down to VSS for correct operation. PCI Interrupt (Active-Low). PCI Reset (Active-Low). PCI Grant Signal (Active-Low). PCI Request Signal (Active-Low). PCI Power Management Event (Active-Low). Power. PCI Clock Input. 33 MHz. Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Power. Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Ground. PCI Command/Byte Enable (Active-Low). PCI ID Select. PCI Address/Data Bit. Agere Systems Inc.
4 5 6
NC CNA NANDTREE
-- O O
7 8 9 10 11 12 13
TEST1 ROM_CLK ROM_AD TEST0 VDD VSS CLKRUNN
I I/O I/O I -- -- I/O
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 14
PCI_INTAN PCI_RSTN PCI_GNTN PCI_REQN PCI_PMEN VDD PCI_CLK VSS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD VSS PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] VSS PCI_CBEN[3] PCI_IDSEL PCI_AD[23]
O I I O O -- I -- I/O I/O I/O I/O -- -- I/O I/O I/O I/O -- I/O I I/O
* Active-low signals within this document are indicated by an N following the symbol names.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Symbol* PCI_AD[22] VDD VSS PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] VDD VSS PCI_AD[17] PCI_AD[16] PCI_CBEN[2] PCI_FRAMEN VDD VSS PCI_IRDYN PCI_TRDYN PCI_DEVSELN PCI_STOPN VDD VSS PCI_PERRN PCI_SERRN PCI_PAR PCI_CBEN[1] VSS PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] VSS PCI_AD[11] PCI_AD[10] PCI_AD[9] PCI_AD[8] VSS VDD PCI_CBEN[0] PCI_AD[7] PCI_AD[6] PCI_AD[5] VSS PCI_AD[4] Type I/O -- -- I/O I/O I/O I/O -- -- I/O I/O I/O I/O -- -- I/O I/O I/O I/O -- -- I/O I/O I/O I/O -- I/O I/O I/O I/O -- I/O I/O I/O I/O -- -- I/O I/O I/O I/O -- I/O Description PCI Address/Data Bit. Power. Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Power. Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Command/Byte Enable Signal (Active-Low). PCI Frame Signal (Active-Low). Power. Ground. PCI Initiator Ready Signal (Active-Low). PCI Target Ready Signal (Active-Low). PCI Device Select Signal (Active-Low). PCI Stop Signal (Active-Low). Power. Ground. PCI Parity Error Signal (Active-Low). PCI System Error Signal (Active-Low). PCI Parity Signal. PCI Command/Byte Enable Signal (Active-Low). Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Ground. Power. PCI Command/Byte Enable Signal (Active-Low). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Ground. PCI Address/Data Bit.
* Active-low signals within this document are indicated by an N following the symbol names.
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 79 80 81 82 83 84 85 86 Symbol* PCI_AD[3] PCI_AD[2] VSS VDD PCI_AD[1] PCI_AD[0] PCI_VIOS CONTENDER Type I/O I/O -- -- I/O I/O -- I Description PCI Address/Data Bit. PCI Address/Data Bit. Ground. Power. PCI Address/Data Bit. PCI Address/Data Bit. PCI Signaling Indicator. (5 V or 3.3 V.) Contender. On hardware reset, this input sets the default value of the CONTENDER bit indicated during self-ID. This bit can be programmed by tying the signal to VDD (high) or to ground (low). Power-Class Indicators. On hardware reset, these inputs set the default value of the power class indicated during self-ID. These bits can be programmed by tying the signals to VDD (high) or to ground (low). Link On. Signal from the internal PHY core to the internal link core. This signal is provided as an output for use in legacy power management systems. Link Power Status. Signal from the internal link core to the internal PHY core. LPS is provided as an output for use in legacy power management systems. No Connect. Power. Cable Power Status. CPS is normally connected to the cable power through a 400 k resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in one internal register and is available to the LLC by way of a register read (see IEEE 1394a-2000, Standard for a High Performance Serial Bus (Supplement)). Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Power. VDDA supplies power to the analog portion of the device. Port 2, Port Cable Pair B. TPB2 is the port B connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Port 2, Port Cable Pair A. TPA2 is the port A connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector.
87 88 89 90
PC2 PC1 PC0 LKON
I
O
91
LPS
O
92 93 94
NC VDD CPS
-- -- I
95 96 97 98
VSSA VDDA TPB2TPB2+
-- -- Analog I/O
99 100
TPA2TPA2+
Analog I/O
* Active-low signals within this document are indicated by an N following the symbol names.
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 101 Symbol* TPBIAS2 Type Analog I/O Description Port 2, Twisted-Pair Bias. TPBIAS2 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Ground. VDDA supplies power to the analog portion of the device. Port 1, Port Cable Pair B. TPB1 is the port B connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Port 1, Port Cable Pair A. TPA1 is the port A connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Port 1, Twisted-Pair Bias. TPBIAS1 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. Port 0, Port Cable Pair B. TPB0 is the port B connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Port 0, Port Cable Pair A. TPA0 is the port A connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. Port 0, Twisted-Pair Bias. TPBIAS0 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Power. VDDA supplies power to the analog portion of the device.
102 103 104 105 106
VSSA VSSA VDDA TPB1- TPB1+
-- -- -- Analog I/O
107 108
TPA1- TPA1+
Analog I/O
109
TPBIAS1
Analog I/O
110 111
TPB0- TPB0+
Analog I/O
112 113
TPA0- TPA0+
Analog I/O
114
TPBIAS0
Analog I/O
115 116
VSSA VDDA
-- --
* Active-low signals within this document are indicated by an N following the symbol names.
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued) Pin 117 Symbol* R0 Type I Description Current Setting Resistor. An internal reference voltage is applied to a resistor connected between R0 and R1 to set the operating current and the cable driver output current. A low temperature-coefficient resistor (TCR) with a value of 2.49 k 1% should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry portion of the device. Ground for PLL Circuit. PLLVSS is tied to a lowimpedance ground plane. Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant fundamental mode crystal. Although when a 24.576 MHz clock source is used, it can be connected to XI with XO left unconnected. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. The suggested values of 12 pF are appropriate for crystal with 7 pF specified loads. For more details, see the Crystal Selection Considerations section. Reset (Active-Low). When RESETN is asserted low (active), a bus reset condition is set on the active cable ports and the internal PHY core logic is reset to the reset start state. An internal pull-up resistor, which is connected to VDD, is provided, so only an external delay capacitor and resistor are required. This input is a standard logic buffer and can also be driven by an open-drain logic output buffer. Test. Used for device testing. Tie to VSS. Test Mode Control. SM is used during the manufacturing test and should be tied to VSS. Test Mode Control. SE is used during the manufacturing test and should be tied to VSS. No Connect. No Connect.
118
R1
119 120 121
PLLVDD PLLVSS XI
-- -- --
122
XO
123
RESETN
I
124 125 126 127 128
PTEST SM SE NC NC
I I I -- --
* Active-low signals within this document are indicated by an N following the symbol names.
Application Schematic
The application schematic presents a complete three-port, 400 Mbits/s IEEE 1394a-2000 design, featuring the Agere FW323 PCI bus-based host OHCI controller and 400 Mbits/s PHY core. The FW323 device needs only a power source (U3), connection to PCI interface, 1394a-2000 terminators and connectors, crystal, and serial EEPROM. No external PHY is required because the FW323 contains both host controller and PHY core functions. This design is a secondary (Class 4) power provider to the 1394 bus, and will participate in the required 1394a2000 bus activities, even when power on the PCI bus is not energized.
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Application Schematic (continued)
3.3 V 3.3 V 3.3 VA F1 OMNI-BLOCK FUSE BPWR U1 PCI BUS 85 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C_BE#0 C_BE#1 C_BE#2 C_BE#3 PAR FRAME# IRDY# TRDY# DEVSEL# STOP# IDSEL REQ# GNT# PERR# SERR# CLK RST# INTA# PME# 84 83 80 79 78 76 75 74 70 69 68 67 65 64 63 62 46 45 42 41 40 39 36 35 31 30 29 28 25 24 23 22 96 VDDA VDDA 104 VDDA 116 PLLVDD 119 93 82 72 55 49 43 37 26 19 11 1 C3 12 pF 4 Y1 3 24.576 MHz 2 C4 12 pF R4 56.2 1% 1/10 W R5 56.2 1% 1/10 W C1 220 pF R1 56.2 1% 1/10 W R2 56.2 1% 1/10 W R3 4.99 1% 1/10 W AGND 1394A PORT 1 J1 VP AGND 3 VG TPB- 4 TPB+ 5 TPA- 6 TPA+ 1 2 AGND
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
X1
121
PCI_VIOS PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
X0 RESETN
122 123
1
R1
118
C5 0.1 F 510 k R7 2.49 k 1% 1/10 W
C6 0.33 F
AGND BPWR
F2 OMNI-BLOCK FUSE
R0 TPB0- TPB0+ TPA0- TPA0+ TPBIAS0 TPB1- TPB1+ TPA1- TPA1+ TPBIAS1 TPB2- TPB2+ TPA2- TPA2+ TPBIAS2 CPS NC LPS LKON PC0 PC1 PC2 CONTENDER NC NC CARDBUSN NC CNA NANDTREE TEST0 TEST1 PTEST SE SM
117 110 111 112 113 114 105 106 107 108 109 97 98 99 100 101 94 92 91 90 89 88 87 86 128 R13 402 k 1% BPWR C7 220 pF R8 56.2 1% 1/10 W R9 56.2 1% 1/10 W R10 4.99 1% 1/10 W AGND
1394A PORT 2 J2 VP 1 2 AGND
AGND
3 VG TPB- 4 TPB+ 5 TPA- 6 TPA+
R11 56.2 1% 1/10 W
R12 56.2 1% 1/10 W
FW323
C8 0.33 F
AGND BPWR
F3 OMNI-BLOCK FUSE
73 PCI_CBEN0 60 PCI_CBEN1 47 PCI_CBEN2 33 PCI_CBEN3 59 48 51 52 53 54 34 PCI_PAR PCI_FRAMEN PCI_IRDYN PCI_TRDYN PCI_DEVSELN PCI_STOPN PCI_IDSEL
R14 10 k 3.3 V R18 10 k R19 10 k R20 10 k C9 220 pF R15 56.2 1% 1/10 W R16 56.2 1% 1/10 W R17 4.99 1% 1/10 W AGND 1394A PORT 3 J3 VP AGND 3 VG TPB- 4 TPB+ 5 TPA- 6 TPA+ 1 2 AGND
127
3 4 5 6 10 7 124 126 125
17 PCI_REQN 16 PCI_GNTN 57 PCI_PERRN 58 PCI_SERRN 20 PCI_PCLK 13 PCI_CLKRUNN 15 PCI_PRSTN 14 PCI_INTAN 18 PCI_PMEN VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3.3 V
R21 56.2 1% 1/10 W
R22 56.2 1% 1/10 W
R23 10 k ROM_AD ROM_CLK 3.3 V 8 5 U2 VCC SDATA SCLK A0 A1 A2 WP GND 6 1 2 3 7 4
R24 10 k
C11 0.33 F
AGND
ROM_AD ROM_CLK PLLVSS VSSA VSSA VSSA VSSA
9 8
EEPROM
2 12 21 27 32 38 44 50 56 61 66 71 77 81
120 115 103 102 95
AT24C02AN-2.7
AGND CR1 MBRS340T3 BPWR CR2 MBRS340T3 5 V PCI CR4 MBRS340T3 12 V PCI F4 1.5 A RESETTABLE C12 22 F 50 V + U3 SUPPLIES VDDX POWER; IT IS SOURCED BY THE MOST POSITIVE OF PCI 5 V, PCI 12 V, AND 1394 BUS POWER (BPWR). U3 PWRSRC 10 1 2 7 5 4 6 12 VOUT VIN 8 NC NC 9 NC NC 11 NC NC 13 NC ON/OFF 14 NC SIGGND 3 FB PWRGND LM2574HVM-3.3 AGND
3.3 V L1 680 H
3.3 VA
POWER PLANE CR3 MBRS1100T3 C13 100 F 10 V + C14 100 F 10 V + FILTERING GROUND PLANE
5-8886(f) R.05fm
Figure 4. Application Schematic for the FW323
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Internal Registers
This section describes the internal registers in FW323, including both PCI configuration registers and OHCI registers. All registers are detailed in the same format; a brief description for each register, followed by the register offset and a bit table describing the reset state for each register. A bit description table indicates bit-field names, a detailed field description, and field access tags. Table 2 describes the field access tags. Table 2. Bit-Field Access Tag Description Access Tag R W S C U Name Read Write Set Clear Update Description Field may be read by software. Field may be written by software to any value. Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of 1. Writes of 0 have no effect. Field may be autonomously updated by the FW323.
PCI Configuration Registers
Table 3 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user definable registers. Table 3. PCI Configuration Register Map Register Name Device ID Status Class Code BIST Header Type Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved Subsystem ID Reserved Reserved Reserved Maximum Latency Minimum Grant Interrupt Pin Next Item Pointer Reserved Interrupt Line Capability ID PCI OHCI Control Register Power Management Capabilities Pm Data Pmcsr_bse Power Management CSR Capabilities Pointer Subsystem Vendor ID OHCI Registers Base Address Vendor ID Command Revision ID Cache Line Size Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4C--FCh
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the device. The vendor ID assigned to Agere is 11C1h. Table 4. Vendor ID Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1
Register: Type: Offset: Default:
Vendor ID register Read only 00h 11C1h
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Device ID Register
The device ID register contains a value assigned to the FW323 by Agere. The device identification for the FW323 is 5811h. Table 5. Device ID Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Device ID Type R R R R R R R R R R R R R R R R Default 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 1
Register: Type: Offset: Default:
Device ID register Read only 02h 5811h
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
PCI Command Register
The command register provides control over the FW323 interface to the PCI bus. All bit functions adhere to the definitions in the PCI local bus specification, as in the following bit descriptions. Table 6. PCI Command Register Bit Field Name Type Default R R R R R R R RW R RW R RW R RW RW R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 Reserved 14 13 12 11 10 9 FBB_ENB 8 SERR_ENB 7 STEP_ENB 6 PERR_ENB 5 VGA_ENB 4 MWI_ENB 3 SPECIAL 2 MASTER_ENB 1 MEMORY_ENB 0 IO_ENB Register: Type: Offset: Default:
PCI command register Read/write 04h 0000h
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Table 7. PCI Command Register Description Bit 15:10 9 8 Field Name Reserved FBB_ENB SERR_ENB Type R R RW Description Reserved. Bits 15:10 return 0s when read. Fast Back-to-Back Enable. The FW323 does not generate fast backto-back transactions; thus, this bit returns 0 when read. SERR Enable. When this bit is set, the FW323 SERR driver is enabled. SERR can be asserted after detecting an address parity error on the PCI bus. Address/Data Stepping Control. The FW323 does not support address/data stepping; thus, this bit is hardwired to 0. Parity Error Enable. When this bit is set, the FW323 is enabled to drive PERR response to parity errors through the PERR signal. VGA Palette Snoop Enable. The FW323 does not feature VGA palette snooping. This bit returns 0 when read. Memory Write and Invalidate Enable. When this bit is set, the FW323 is enabled to generate MWI PCI bus commands. If this bit is reset, then the FW323 generates memory write commands instead. Special Cycle Enable. The FW323 function does not respond to special cycle transactions. This bit returns 0 when read. Bus Master Enable. When this bit is set, the FW323 is enabled to initiate cycles on the PCI bus. Memory Response Enable. Setting this bit enables the FW323 to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. I/O Space Enable. The FW323 does not implement any I/O mapped functionality; thus, this bit returns 0 when read.
7 6 5 4
STEP_ENB PERR_ENB VGA_ENB MWI_ENB
R RW R RW
3 2 1
SPECIAL MASTER_ENB MEMORY_ENB
R RW RW
0
IO_ENB
R
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
PCI Status Register
The status register provides status over the FW323 interface to the PCI bus. All bit functions adhere to the definitions in the PCI local bus specification, as in the following bit descriptions. Table 8. PCI Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name PAR_ERR SYS_ERR MABORT TABORT_REC TABORT_SIG PCI_SPEED DATAPAR FBB_CAP UDF 66MHZ CAPLIST Reserved Type RCU RCU RCU RCU RCU R R RCU R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
PCI status register Read/clear/update 06h 0210h
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FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Class Code and Revision ID Register
The class code register and revision ID register categorizes the FW323 as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the chip revision is indicated in the lower byte. Table 9. Class Code and Revision ID Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name BASECLASS Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
SUBCLASS
PGMIF
CHIPREV
Register: Type: Offset: Default:
Class code and revision ID register Read only 08h 0C00 1000h
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Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 10. Class Code and Revision ID Register Description Bit 31:24 23:16 15:8 Field Name BASECLASS SUBCLASS PGMIF Type R R R Description Base Class. This field returns 0Ch when read, which classifies the function as a serial bus controller. Subclass. This field returns 00h when read, which specifically classifies the function as an IEEE 1394 serial bus controller. Programming Interface. This field returns 10h when read, indicating that the programming model is compliant with the 1394 Open Host Controller Interface Specification. Silicon Revision. This field returns 04h when read, indicating the silicon revision of the FW323.
7:0
CHIPREV
R
Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the FW323. Table 11. Latency Timer and Class Cache Line Size Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name LATENCY_TIMER Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CACHELINE_SZ
Latency timer and class cache line size register Read/write 0Ch 0000h
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Internal Registers (continued)
Table 12. Latency Timer and Class Cache Line Size Register Description Bit 15:8 Field Name LATENCY_TIMER Type RW Description PCI Latency Timer. The value in this register specifies the latency timer for the FW323, in units of PCI clock cycles. When the FW323 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the FW323 transaction has terminated, then the FW323 terminates the transaction when its GNT is deasserted. Cache Line Size. This value is used by the FW323 during memory write and invalidate, memory read line, and memory read multiple transactions.
7:0
CACHELINE_SZ
RW
Header Type and BIST Register
The header type and BIST register indicates the FW323 PCI header type, and indicates no built-in self-test. Table 13. Header Type and BIST Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HEADER_TYPE
Header type and BIST register Read only 0Eh 0000h
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Internal Registers (continued)
Table 14. Header Type and BIST Register Description Bit 15:8 7:0 Field Name BIST HEADER_TYPE Type R R Description Built-In Self-Test. The FW323 does not include a built-in self-test; thus, this field returns 00h when read. PCI Header Type. The FW323 includes the standard PCI header, and this is communicated by returning 00h when this field is read.
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Internal Registers (continued)
OHCI Base Address Register
The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4K bytes of memory address space are required for the OHCI registers. Table 15. OHCI Base Address Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R R R R R R R Type OHCIREG_PTR Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OHCI_SZ
OHCI_PF OHCI_MEMTYPE OHCI_MEM
Register: Type: Offset: Default:
OHCI base address register Read/write 10h 0000 0000h
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Internal Registers (continued)
Table 16. OHCI Base Address Register Description Bit 31:12 11:4 3 2:1 Field Name OHCIREG_PTR OHCI_SZ OHCI_PF OHCI_MEMTYPE Type RW R R R Description OHCI Register Pointer. Specifies the upper 20 bits of the 32-bit OHCI base address register. OHCI Register Size. This field returns 0s when read, indicating that the OHCI registers require a 4 Kbyte region of memory. OHCI Register Prefetch. This bit returns 0 when read, indicating that the OHCI registers are nonprefetchable. OHCI Memory Type. This field returns 0s when read, indicating that the OHCI base address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. OHCI Memory Indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped into system memory space.
0
OHCI_MEM
R
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Internal Registers (continued)
PCI Subsystem Identification Register
The PCI subsystem identification register is used to uniquely identify the card or system in which the FW323 resides. These values are loaded from the serial EEPROM during the power-up sequence. Table 17. PCI Subsystem Identification Register Description Bit 31:16 15:0 Field Name SSID SSVID Type RU RU Description Subsystem ID. This field indicates the subsystem ID. Subsystem Vendor ID. This field indicates the subsystem vendor ID.
PCI Power Management Capabilities Pointer Register
The PCI power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. The FW323 configuration words at offsets 44h and 48h provide the power management registers. This register is read only and returns 44h when read. Table 18. PCI Power Management Capabilities Pointer Register Bit 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Type R R R R R R R R Default 0 1 0 0 0 1 0 0
PCI power management capabilities pointer register Read only 34h 44h
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Internal Registers (continued)
Interrupt Line and Pin Register
The interrupt line and pin register is used to communicate interrupt line routing information. Table 19. Interrupt Line and Pin Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name INTR_PIN Type R R R R R R R R RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
INTR_LINE
Interrupt line and pin register Read/write 3Ch 0100h
Table 20. Interrupt Line and Pin Register Description Bit 15:8 7:0 Field Name INTR_PIN INTR_LINE Type R RW Description Interrupt Pin Register. This register returns 01h when read, indicating that the FW323 PCI function signals interrupts on the INTA pin. Interrupt Line Register. This register is programmed by the system and indicates to software to which interrupt line the FW323 INTA is connected.
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Internal Registers (continued)
MIN_GNT and MAX_LAT Register
The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the latency timer register. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 0C, MAX_LAT = 18. Table 21. MIN_GNT and MAX_LAT Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name MAX_LAT Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0
MIN_GNT
MIN_GNT and MAX_LAT register Read/update 3Eh 180C
Table 22. MIN_GNT and MAX_LAT Register Description Bit 15:8 Field Name MAX_LAT Type RU Description Maximum Latency. The contents of this register may be used by host BIOS to assign an arbitration priority level to the FW323. The default for this register indicates that the FW323 may need to access the PCI bus as often as every 0.25 s; thus, an extremely high priority level is requested. The contents of this field may also be loaded through the serial ROM. Minimum Grant. The contents of this register may be used by host BIOS to assign a latency timer register value to the FW323. The default for this register indicates that the FW323 may need to sustain burst transfers for nearly 64 s; thus, requesting a large value be programmed in the FW323 latency timer register.
7:0
MIN_GNT
RU
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Internal Registers (continued)
PCI OHCI Control Register
The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. Note that the GLOBAL_SWAP bit is loaded from the serial EEPROM on powerup. Table 23. PCI OHCI Control Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GLOBAL_SWAP
Register: Type: Offset: Default:
PCI OHCI control register Read/write 40h 0000 0000h
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Internal Registers (continued)
Table 24. PCI OHCI Control Register Description Bit 31:1 0 Field Name Reserved GLOBAL_SWAP Type R RW Description Reserved. Bits 31:1 return 0s when read. When this bit is set, all quadlets read from and written to the PCI interface are byte swapped.
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Internal Registers (continued)
Capability ID and Next Item Pointer Register
The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item. Table 25. Capability ID and Next Item Pointer Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name NEXT_ITEM Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
CAPABILITY_ID
Capability ID and next item pointer register Read only 44h 0001h
Table 26. Capability ID and Next Item Pointer Register Description Bit 15:8 Field Name NEXT_ITEM Type R Description Next Item Pointer. The FW323 supports only one additional capability that is communicated to the system through the extended capabilities list; thus, this field returns 00h when read. Capability Identification. This field returns 01h when read, which is the unique ID assigned by the PCI SIG for PCI power management capability.
7:0
CAPABILITY_ID
R
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Internal Registers (continued)
Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the FW323 related to PCI power management. Table 27. Power Management Capabilities Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name PME_D3COLD PME_D3HOT PME_D2 PME_D1 PME_D0 D2_SUPPORT D1_SUPPORT DYN_DATA Reserved DSI AUX_PWR PME_CLK PM_VERSION Type R R R R R R R R R R R R R R R R Default 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0
Power management capabilities register Read/update 46h 7E02h
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Internal Registers (continued)
Table 28. Power Management Capabilities Register Description Bit 15 14 13 12 11 10 9 8 7:6 5 Field Name PME_D3COLD PME_D3HOT PME_D2 PME_D1 PME_D0 D2_SUPPORT D1_SUPPORT DYN_DATA Reserved DSI Type R R R R R R R R R R Description PME Support from D3 COLD. Set to 0, indicating the FW323 will not generate a PME event in the D3 COLD state. PME Support From D3 HOT. Set to 1, indicating that the FW323 can generate a PME event in the D3 HOT state. PME Support From D2. Set to 1, indicating that the FW323 can generate a PME in D2. PME Support From D1. Set to 1, indicating that the FW323 can generate a PME in D1. PME Support From D0. Set to 1, indicating that the FW323 can generate a PME in D0. D2 Support. This bit returns a 1 when read, indicating that the FW323 supports the D2 power state. D1 Support. This bit returns a 1 when read, indicating that the FW323 supports the D1 power state. Dynamic Data Support. This bit returns a 0 when read, indicating that the FW323 does not report dynamic power consumption data. Reserved. Bits 7:6 return 0s when read. Device-Specific Initialization. This bit returns 0 when read, indicating that the FW323 does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it. Auxiliary Power Source. Since the FW323 does not support PME generation in the D3 COLD device state, this bit returns 0 when read. PME Clock. This bit returns 0 when read, indicating that no host bus clock is required for the FW323 to generate PME. Power Management Version. This field returns 010b when read, indicating that the FW323 is compatible with the registers described in the PCI Power Management Interface Specification, Rev.1.1.
4 3 2:0
AUX_PWR PME_CLK PM_VERSION
R R R
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Internal Registers (continued)
Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3 HOT to D0 state. Table 29. Power Management Control and Status Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name PME_STS DATA_SCALE DATA_SELECTED Type RC R R R R R R RW R R R R R R RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PME_ENB Reserved
DYN_DATA Reserved PWR_STATE
Power management control and status register Read/write/clear 48h 0000h
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Internal Registers (continued)
Table 30. Power Management Control and Status Register Description Bit 15 Field Name PME_STS Type RC Description
14:13 12:9 8 7:5 4 3:2 1:0
DATA_SCALE DATA_SELECTED PME_ENB Reserved DYN_DATA Reserved PWR_STATE
This bit is set when the FW323 would normally be asserting the PME signal, independent of the state of the PME_ENB bit. This bit is cleared by a writeback of 1, and this also clears the PME signal driven by the FW323. Writing a 0 to this bit has no effect. R This field returns 0s when read, since the FW323 does not report dynamic data. R This field returns 0s when read, since the FW323 does not report dynamic data. RW PME Enable. This bit enables the function to assert PME. If this bit is cleared, then assertion of PME is disabled. R Reserved. Bits 7:5 return 0s when read. R Dynamic Data. This bit returns 0 when read, since the FW323 does not report dynamic data. R Reserved. Bits 3:2 return 0s when read. RW Power State. This 2-bit field is used to set the FW323 device power state and is encoded as follows: 00 = current power state is D0. 01 = current power state is D1. 10 = current power state is D2. 11 = current power state is D3.
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Internal Registers (continued)
Power Management Extension Register
The power management extension register provides extended power management features not applicable to the FW323; thus, it is read only and returns 0 when read. Table 31. Power Management Extension Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name PM_DATA Type R R R R R R R R RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMCSR_BSE
Power management extension register Read only 4Ah 0000h
Table 32. Power Management Extension Register Description Bit 15:8 7:0 Field Name PM_DATA PMCSR_BSE Type R R Description Power Management Data. This field returns 00h when read since the FW323 does not report dynamic data. Power Management CSR Bridge Support Extensions. This field returns 00h when read since the FW323 does not provide P2P bridging.
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Internal Registers (continued)
OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a 2 Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space. These registers are the primary interface for controlling the FW323 IEEE 1394 OHCI function. This section provides the register interface and bit descriptions. There are several set and clear register pairs in this programming model, which are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 33 for an illustration. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be reset, while a 0 bit leaves the corresponding bit in the set/clear register unaffected. Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior. The following register definitions are based on version 1.0 of the 1394 Open Host Controller Specification. These definitions do not include any incremental changes or additions defined in version 1.1 of the 1394 Open Host Controller Specification. The version 1.1 changes and additions will be included in a future revision of this data sheet. Table 33. OHCI Register Map DMA Context -- Register Name OHCI version Global unique ID ROM Asynchronous transmit retries CSR data CSR compare data CSR control Configuration ROM header Bus identification Bus options Global unique ID high Global unique ID low PCI subsystem identification Reserved Configuration ROM map Posted write address low Posted write address high Vendor identification Capability ID and next item pointer Power management capabilities Power management control and status Power management extensions Reserved Host controller control Reserved Reserved Abbreviation Version GUID_ROM ATRetries CSRData CSRCompareData CSRControl ConfigROMhdr BusID BusOptions GUIDHi GUIDLo SSID -- ConfigROMmap PostedWriteAddressLo PostedWriteAddressHi VendorID CAP_ID PM_CAP PMCSR PM_Ext -- HCControlSet HCControlClr -- -- Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 46h 48h 4Ah 4Ch 50h 54h 58h 5Ch
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Internal Registers (continued)
Table 33. OHCI Register Map (continued) DMA Context Self-ID Register Name Reserved Self-ID buffer Self-ID count Reserved Isochronous receive channel mask high Isochronous receive channel mask low Interrupt event Interrupt mask Isochronous transmit interrupt event Isochronous transmit interrupt mask -- Isochronous receive interrupt event Isochronous receive interrupt mask Reserved Fairness control Link control Node identification PHY core layer control Isochronous cycle timer Reserved Reserved Reserved Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low Physical upper bound Reserved Abbreviation -- SelfIDBuffer SelfIDCount -- IRChannelMaskHiSet IRChannelMaskHiClear IRChannelMaskLoSet IRChannelMaskLoClear IntEventSet IntEventClear IntMaskSet IntMaskClear IsoXmitIntEventSet IsoXmitIntEventClear IsoXmitIntMaskSet IsoXmitIntMaskClear IsoRecvIntEventSet IsoRecvIntEventClear IsoRecvIntMaskSet IsoRecvIntMaskClear -- FairnessControl LinkControlSet LinkControlClear NodeID PhyControl IsoCycTimer -- -- -- AsyncRequestFilterHiSet AsyncRequestFilterHiClear AsyncRequestFilterLoSet AsyncRequestFilterloClear PhysicalRequestFilterHiSet PhysicalRequestFilterHiClear PhysicalRequestFilterLoSet PhysicalRequestFilterloClear PhysicalUpperBound -- Offset 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 8Ch 90h 94h 98h 9Ch A0h A4h A8h ACh B0h:D8h DCh E0h E4h E8h ECh F0h F4h F8h FCh 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h:17Ch
--
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Internal Registers (continued)
Table 33. OHCI Register Map (continued) DMA Context Asychronous Request Transmit [ATRQ] Asychronous Response Transmit [ATRS] Register Name Context control Reserved Command pointer Reserved Context control Reserved Command pointer Reserved Context control Reserved Command pointer Reserved Context control Reserved Command pointer Reserved Context control Reserved Command pointer Context control Reserved Command pointer Context match Abbreviation ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr -- ContextControlSet ContextControlClear -- CommandPtr ContextControlSet ContextControlClear -- CommandPtr ContextMatch Offset 180h 184h 188h 18Ch 190h--19Ch 1A0h 1A4h 1A8h 1ACh 1B0h--1BCh 1C0h 1C4h 1C8h 1CCh 1D0h--1DCh 1E0h 1E4h 1E8h 1ECh 1F0h--1FCh 200h + 16 * n 204h + 16 * n 208h + 16 * n 20Ch + 16 * n 400h + 32 * n 404h + 32 * n 408h + 32 * n 40Ch + 32 * n 410h + 32 * n
Asychronous Request Receive [ARRQ]
Asychronous Response Receive [ARRS]
Isochronous Transmit Context n n = 0:7
Isochronous Receive Context n n = 0:7
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Internal Registers (continued)
OHCI Version Register
This register indicates the OHCI version support, and whether or not the serial ROM is present. Table 34. OHCI Version Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GUID_ROM Version
Reserved
Revision
OHCI version register Read only 00h 0X01 0000h
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Internal Registers (continued)
Table 35. OHCI Version Register Description Bit 31:25 24 Field Name Reserved GUID_ROM Type R R Description Reserved. Bits 31:25 return 0s when read. The FW323 sets this bit if the serial ROM is detected. If the serial ROM is present, then the Bus_Info_Block and chip configuration data is automatically loaded on hardware reset. Major Version of the OHCI. The FW323 is compliant with the 1394 Open Host Controller Interface Specification; thus, this field reads 01h. Reserved. Bits 15:8 return 0s when read. Minor Version of the OHCI. The FW323 is compliant with the 1394 Open Host Controller Interface Specification; thus, this field reads 00h.
23:16
Version
R
15:8 7:0
Reserved Revision
R R
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Internal Registers (continued)
GUID ROM Register
The GUID ROM register is used to access the serial ROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register is set. Table 36. GUID ROM Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name addrReset Reserved Type RSU R R R R R RSU R RU RU RU RU RU RU RU RU R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rdStart Reserved rdData
Reserved
GUID ROM register Read/set/update 04h 00XX 0000h
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Internal Registers (continued)
Table 37. GUID ROM Register Description Bit 31 30:26 25 Field Name addrReset Reserved rdStart Type RSU R RSU Description Software sets this bit to reset the GUID ROM address to 0. When the FW323 completes the reset, it clears this bit. Reserved. Bits 30:26 return 0s when read. A read of the currently addressed byte is started when this bit is set. This bit is automatically cleared when the FW323 completes the read of the currently addressed GUID ROM byte. Reserved. Bit 24 returns 0 when read. This field represents the data read from the GUID ROM and is only valid when rdStart = 0. Reserved. Bits 15:0 return 0s when read.
24 23:16 15:0
Reserved rdData Reserved
R RU R
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Internal Registers (continued)
Asynchronous Transmit Retries Register
The asynchronous transmit retries register indicates the number of times the FW323 attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. Table 38. Asynchronous Transmit Retries Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name secondLimit Type R R R R R R R R R R R R R R R R R R R R RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cycleLimit
Reserved
maxPhysRespRetries
maxATRespRetries
maxATReqRetries
Asynchronous transmit retries register Read/write 08h 0000 0000h
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Internal Registers (continued)
Table 39. Asynchronous Transmit Retries Register Description Bit 31:29 28:16 15:12 11:8 Field Name secondLimit cycleLimit Reserved maxPhysRespRetries Type R R R RW Description The second limit field returns 0s when read, since outbound dualphase retry is not implemented. The cycle limit field returns 0s when read, since outbound dualphase retry is not implemented. Reserved. Bits 15:12 return 0s when read. This field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. This field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node. This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node.
7:4
maxATRespRetries
RW
3:0
maxATReqRetries
RW
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Internal Registers (continued)
CSR Data Register
The CSR data register is used to access the bus management CSR registers from the host through compareswap operations. This register contains the data to be stored in a CSR if the compare is successful. Table 40. CSR Data Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name csrData Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CSR data register Read only 0Ch XXXX XXXXh
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Internal Registers (continued)
Table 41. CSR Data Register Description Bit 31:0 Field Name csrData Type RWU Description At start of operation, the data to be stored if the compare is successful.
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Internal Registers (continued)
CSR Compare Register
The CSR compare register is used to access the bus management CSR registers from the host through compareswap operations. This register contains the data to be compared with the existing value of the CSR resource. Table 42. CSR Compare Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name csrCompare Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
CSR compare register Read only 10h XXXX XXXXh
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Internal Registers (continued)
Table 43. CSR Compare Register Description Bit 31:0 Field Name csrCompare Type RW Description The data to be compared with the existing value of the CSR resource.
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Internal Registers (continued)
CSR Control Register
The CSR compare register is used to access the bus management CSR registers from the host through compareswap operations. This register contains the data to be compared with the existing value of the CSR resource. Table 44. CSR Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name csrDone Reserved Type RU R R R R R R R R R R R R R R R R R R R R R R R R R R R R R RW RW Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X
csrSel
CSR control register Read/write/update 14h 8000 000Xh
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Internal Registers (continued)
Table 45. CSR Control Register Description Bit 31 30:2 1:0 Field Name csrDone Reserved csrSel Type RU R RW Description This bit is set by the FW323 when a compare-swap operation is complete. It is reset whenever this register is written. Reserved. Bits 30:2 return 0s when read. This field selects the CSR resource as follows: 00 = BUS_MANAGER_ID 01 = BANDWIDTH_AVAILABLE 10 = CHANNELS_AVAILABLE_HI 11 = CHANNELS_AVAILABLE_LO
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset 48'hFFFF_F000_0400. Table 46. Configuration ROM Header Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name info_length Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X X X X X X X
crc_length
rom_crc_value
Configuration ROM header register Read/write 18h 0000 0000h
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Internal Registers
Table 47. Configuration ROM Header Register Description Bit 31:24 23:16 15:0 Field Name info_length crc_length rom_crc_value Type RW RW RW Description
IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. IEEE 1394 Bus Management Field. Must be valid at any time bit 17 (linkEnable) of the host controller control register is set. If a serial ROM is present, then this field is loaded from the serial ROM.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Bus Identification Register
The bus identification register externally maps to the first quadlet in the Bus_Info_Block, 1394 addressable at FFFF_F000_0404. Table 48. Bus Identification Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name busID Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 0 0 1 1 0 1 0 0
Bus identification register Read only 1Ch 3133 3934h
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Internal Registers (continued)
Table 49. Bus Identification Register Description Bit 31--0 Field Name busID Type R Description Contains the constant 32'h31333934, which is the ASCII value for 1394.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block, 1394 addressable at FFFF_F000_0408. Table 50. Bus Options Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field irmc cmc isc bmc pmc Reserved Type RW RW RW RW RW R R R RW RW RW RW RW RW RW RW RW RW RW RW R R R R RW RW R R R R R R Default X X X X 0 0 0 0 X X X X X X X X 1 0 1 0 0 0 0 0 X X 0 0 0 0 1 0
cyc_clk_acc
max_rec
Reserved
g Reserved
Lnk_spd
Bus options register Read/write 20h 0000 A002h
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Data Sheet, Rev. 2 October 2001
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Internal Registers (continued)
Table 51. Bus Options Register Description Bit 31 Field Name irmc Type RW Description Isochronous Resource Manager Capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. Cycle Master Capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. Isochronous Support Capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. Bus Manager Capable. IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. IEEE 1394 Bus Management Field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. Reserved. Bits 26:24 return 0s when read. Cycle Master Clock Accuracy. (Accuracy in parts per million.) IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control register is set. IEEE 1394 Bus Management Field. Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation. This value, max_rec_bytes, must be 512 greater and is calculated by 2(max_rec + 1). Software may change this field; however, this field must be valid at any time bit 17 (linkEnable) of the host controller control register is set. A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error. This field is not affected by a soft reset, and defaults to value indicating 2048 bytes on a hard reset. Reserved. Bits 11:8 return 0s when read. Generation Counter. This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset. Reserved. Bits 5:3 return 0s when read. Link Speed. This field returns 010, indicating that the link speeds of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s are supported.
30
cmc
RW
29
isc
RW
28
bmc
RW
27 26:24 23:16
pmc Reserved cyc_clk_acc
RW R RW
15:12
max_rec
RW
11:8 7:6
Reserved g
R RW
5:3 2:0
Reserved Lnk_spd
R R
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
GUID High Register
The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third quadlet in the Bus_Info_Block 1394 addressable at FFFF_F000_0410. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a hardware reset, which is an illegal GUID value. If a serial ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset. At that point, the contents of this register cannot be changed. If no serial ROM is detected, then the contents of this register can be loaded with a PCI configuration write to offset 0x80. At that point, the contents of this register cannot be changed. Table 52. GUID High Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name node_vendor_ID Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
chip_ID_hi
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Internal Registers (continued)
Register: Type: Offset: Default: GUID high register Read only 24h 0000 0000h
Table 53. GUID High Register Description Bit 31:8 7:0 Field Name node_vendor_ID chip_ID_hi Type R R Description
IEEE 1394 Bus Management Fields.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
GUID Low Register
The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID), which maps to chip_ID_lo in the Bus_Info_Block 1394 addressable at FFFF_F000_0414. This register initializes to 0s on a hardware reset and behaves identical to the GUID high register. If no serial ROM is detected, then the contents of this register can be loaded with a PCI configuration write to offset 0x84. Table 54. GUID Low Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: 66 Field Name CHIP_ID_lo Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GUID low register Read only 28h 0000 0000h Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
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Internal Registers (continued)
Table 55. GUID Low Register Description Bit 31:0 Field Name chip_ID_lo Type R Description
IEEE 1394 Bus Management Fields.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Configuration ROM Mapping Register
The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. Table 56. Configuration ROM Mapping Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name configROMaddr Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
Configuration ROM mapping register Read/write 34h 0000 0000h
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Data Sheet, Rev. 2 October 2001
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Internal Registers (continued)
Table 57. Configuration ROM Mapping Register Description Bit 31:10 Field Name configROMaddr Type RW Description If a quadlet read request to 1394 offset 48'hFFFF_F000_0400 through offset 48'hFFFF_F000_07FF is received, then the loworder 10 bits of the offset are added to this register to determine the host memory address of the read request. Reserved. Bits 9:0 return 0s when read.
9:0
Reserved
R
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Posted Write Address Low Register
The posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Table 58. Posted Write Address Low Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name offsetLo Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Posted write address low register Read/update 38h XXXX XXXXh
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Internal Registers (continued)
Table 59. Posted Write Address Low Register Description Bit 31:0 Field Name offsetLo Type RU Description The lower 32 bits of the 1394 destination offset of the write request that failed.
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Internal Registers (continued)
Posted Write Address High Register
The posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet. Table 60. Posted Write Address High Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name sourceID Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
offsetHi
Posted write address high register Read/update 3Ch XXXX XXXXh
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Internal Registers (continued)
Table 61. Posted Write Address High Register Description Bit 31:16 15:0 Field Name sourceID offsetHi Type RU RU Description This field is the bus and node number of the node that issued the write request that failed. The upper 16 bits of the 1394 destination offset of the write request that failed.
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Internal Registers (continued)
Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. Table 62. Vendor ID Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name VendorUnique Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VendorCompanyID
Vendor ID register Read only 40h 0000 0000h
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Internal Registers (continued)
Table 63. Vendor ID Register Description Bit 31:24 23:0 Field Name vendorUnique vendorCompanyID Type R R Description Returns 0 when read, since the FW323 does not specify any vendor unique registers. Returns 0 when read, since the FW323 does not specify any vendor unique registers.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the OHCI portion of the FW323. Table 64. Host Controller Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name Reserved noByteSwapData Reserved Type R RSC R R R R R R RC RSC R R RS RSC RSU RSU R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
programPhyEnable aPhyEnhancedEnable Reserved LPS postedWriteEnable linkEnable SoftReset Reserved
Host controller control register Read/set/clear/update 50h set register 54h clear register X00X 0000h
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Internal Registers (continued)
Table 65. Host Controller Control Register Description Bit 31 30 Field Name Reserved noByteSwapData Type R RSC Description Reserved. Bit 31 returns 0 when read. This bit is used to control byte swapping during host bus accesses involving the data portion of 1394 packets. Data is swapped if equal to 0, not swapped when equal to 1. Reserved. Bits 29:24 return 0s when read. This bit informs upper-level software that lower-level software has consistently configured the 1394a-2000 enhancements in the link and PHY core. When this bit is 1, generic software such as the OHCI driver is responsible for configuring 1394a-2000 enhancements in the PHY core and bit 22 (aPhyEnhanceEnable) in the FW323. When this bit is 0, the generic software may not modify the 1394a-2000 enhancements in the FW323 and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from serial EEPROM. When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set this bit to use all 1394a-2000 enhancements. When bit 23 (programPhyEnable) is set to 0, the software does not change PHY enhancements or this bit. Reserved. Bits 21:20 return 0s when read. Link Power Status. This bit drives the LPS signal to the PHY core within the FW323. This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only when bit 17 (linkEnable) is 0. This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset. This bit is necessary to keep other nodes from sending transactions before the local system is ready. When this bit is cleared, the FW323 is logically and immediately disconnected from the 1394 bus, no packets are received or processed, nor are packets transmitted. When this bit is set, all FW323 states are reset, all FIFOs are flushed, and all OHCI registers are set to their hardware reset values unless otherwise specified. PCI registers are not affected by this bit. This bit remains set while the softReset is in progress and reverts back to 0 when the reset has completed. Reserved. Bits 15:0 return 0s when read.
29:24 23
Reserved programPhyEnable
R RC
22
aPhyEnhanceEnable
RSC
21:20 19 18 17
Reserved LPS postedWriteEnable linkEnable
R RS RSC RSU
16
SoftReset
RSU
15:0
Reserved
R
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
The self-ID buffer pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31:11 are read/write accessible. Table 66. Self-ID Buffer Pointer Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name SelfIDBufferPtr Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R R R R R R R R R Default X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0
Reserved
Self-ID buffer pointer register Read/write 64h XXXX XX00h
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Internal Registers (continued)
Table 67. Self-ID Buffer Pointer Register Description Bit 31:11 10:0 Field Name SelfIDBufferPtr Reserved Type RW R Description Contains the 2 Kbyte aligned base address of the buffer in host memory where received self-ID packets are stored. Reserved.
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Internal Registers (continued)
Self-ID Count Register
The self-ID buffer pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the self-ID packets are stored during bus initialization. Bits 31:11 are read/write accessible. Table 68. Self-ID Count Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name selfIDError Reserved Type RU R R R R R R R RU RU RU RU RU RU RU RU R R R R R RU RU RU RU RU RU RU RU RU R R Default X 0 0 0 0 0 0 0 X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
selfIDGeneration
Reserved
selfIDSize
Reserved
Self-ID count register Read/write 68h X0XX 0000h
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Internal Registers (continued)
Table 69. Self-ID Count Register Description Bit 31 Field Name selfIDError Type RU Description When this bit is 1, an error was detected during the most recent self-ID packet reception. The contents of the self-ID buffer are undefined. This bit is cleared after a self-ID reception in which no errors are detected. Note that an error can be a hardware error or a host bus write error. Reserved. Bits 30:24 return 0s when read. The value in this field increments each time a bus reset is detected. This field rolls over to 0 after reaching 255. Reserved. Bits 15:11 return 0s when read. This field indicates the number of quadlets that have been written into the self-ID buffer for the current bits 23:16 (selfIDGeneration field). This includes the header quadlet and the self-ID data. This field is cleared to 0 when the self-ID reception begins. Reserved. Bits 1:0 return 0s when read.
30:24 23:16 15:11 10:2
Reserved selfIDGeneration Reserved selfIDSize
R RU R RU
1:0
Reserved
R
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Internal Registers (continued)
Isochronous Receive Channel Mask High Register
The isochronous receive channel mask high set/clear register is used to enable packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. Table 70. Isochronous Receive Channel Mask High Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: 82 Field Name isoChannel63 isoChannel62 isoChannel61 isoChannel60 isoChannel59 isoChannel58 isoChannel57 isoChannel56 isoChannel55 isoChannel54 isoChannel53 isoChannel52 isoChannel51 isoChannel50 isoChannel49 isoChannel48 isoChannel47 isoChannel46 isoChannel45 isoChannel44 isoChannel43 isoChanne42l isoChannel41 isoChannel40 isoChannel39 isoChannel38 isoChannel37 isoChannel36 isoChannel35 isoChannel34 isoChannel33 isoChannel32 Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Isochronous receive channel mask high register Read/set/clear 70h set register 74h clear register XXXX XXXXh Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Table 71. Isochronous Receive Channel Mask High Register Description Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name isoChannel63 isoChannel62 isoChannel61 isoChannel60 isoChannel59 isoChannel58 isoChannel57 isoChannel56 isoChannel55 isoChannel54 isoChannel53 isoChannel52 isoChannel51 isoChannel50 isoChannel49 isoChannel48 isoChannel47 isoChannel46 isoChannel45 isoChannel44 isoChannel43 isoChannel42 isoChannel41 isoChannel40 isoChannel39 isoChannel38 isoChannel37 isoChannel36 isoChannel35 isoChannel34 isoChannel33 isoChannel32 Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Description If bit 31 is set, iso channel number 63 is enabled. If bit 30 is set, iso channel number 62 is enabled. If bit 29 is set, iso channel number 61 is enabled. If bit 28 is set, iso channel number 60 is enabled. If bit 27 is set, iso channel number 59 is enabled. If bit 26 is set, iso channel number 58 is enabled. If bit 25 is set, iso channel number 57 is enabled. If bit 24 is set, iso channel number 56 is enabled. If bit 23 is set, iso channel number 55 is enabled. If bit 22 is set, iso channel number 54 is enabled. If bit 21 is set, iso channel number 53 is enabled. If bit 20 is set, iso channel number 52 is enabled. If bit 19 is set, iso channel number 51 is enabled. If bit 18 is set, iso channel number 50 is enabled. If bit 17 is set, iso channel number 49 is enabled. If bit 16 is set, iso channel number 48 is enabled. If bit 15 is set, iso channel number 47 is enabled. If bit 14 is set, iso channel number 46 is enabled. If bit 13 is set, iso channel number 45 is enabled. If bit 12 is set, iso channel number 44 is enabled. If bit 11 is set, iso channel number 43 is enabled. If bit 10 is set, iso channel number 42 is enabled. If bit 9 is set, iso channel number 41 is enabled. If bit 8 is set, iso channel number 40 is enabled. If bit 7 is set, iso channel number 39 is enabled. If bit 6 is set, iso channel number 38 is enabled. If bit 5 is set, iso channel number 37 is enabled. If bit 4 is set, iso channel number 36 is enabled. If bit 3 is set, iso channel number 35 is enabled. If bit 2 is set, iso channel number 34 is enabled. If bit 1 is set, iso channel number 33 is enabled. If bit 0 is set, iso channel number 32 is enabled.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Isochronous Receive Channel Mask Low Register
The isochronous receive channel mask low set/clear register is used to enable packet receives from the lower 32 isochronous data channels. Table 72. Isochronous Receive Channel Mask Low Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name isoChannel31 isoChannel30 isoChannel29 isoChannel28 isoChannel27 isoChannel26 isoChannel25 isoChannel24 isoChannel23 isoChannel22 isoChannel21 isoChannel20 isoChannel19 isoChannel18 isoChannel17 isoChannel16 isoChannel15 isoChannel14 isoChannel13 isoChannel12 isoChannel11 isoChannel10 isoChannel9 isoChannel8 isoChannel7 isoChannel6 isoChannel5 isoChannel4 isoChannel3 isoChannel2 isoChannel1 isoChannel0 Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Isochronous receive channel mask low register Read/set/clear 78h set register 7Ch clear register XXXX XXXXh
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Internal Registers (continued)
Table 73. Isochronous Receive Channel Mask Low Register Description Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name isoChannel31 isoChannel30 isoChannel29 isoChannel28 isoChannel27 isoChannel26 isoChannel25 isoChannel24 isoChannel23 isoChannel22 isoChannel21 isoChannel20 isoChannel19 isoChannel18 isoChannel17 isoChannel16 isoChannel15 isoChannel14 isoChannel13 isoChannel12 isoChannel11 isoChannel10 isoChannel9 isoChannel8 isoChannel7 isoChannel6 isoChannel5 isoChannel4 isoChannel3 isoChannel2 isoChannel1 isoChannel0 Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Description If bit 31 is set, iso channel number 31 is enabled. If bit 30 is set, iso channel number 30 is enabled. If bit 29 is set, iso channel number 29 is enabled. If bit 28 is set, iso channel number 28 is enabled. If bit 27 is set, iso channel number 27 is enabled. If bit 26 is set, iso channel number 26 is enabled. If bit 25 is set, iso channel number 25 is enabled. If bit 24 is set, iso channel number 24 is enabled. If bit 23 is set, iso channel number 23 is enabled. If bit 22 is set, iso channel number 22 is enabled. If bit 21 is set, iso channel number 21 is enabled. If bit 20 is set, iso channel number 20 is enabled. If bit 19 is set, iso channel number 19 is enabled. If bit 18 is set, iso channel number 18 is enabled. If bit 17 is set, iso channel number 17 is enabled. If bit 16 is set, iso channel number 16 is enabled. If bit 15 is set, iso channel number 15 is enabled. If bit 14 is set, iso channel number 14 is enabled. If bit 13 is set, iso channel number 13 is enabled. If bit 12 is set, iso channel number 12 is enabled. If bit 11 is set, iso channel number 11 is enabled. If bit 10 is set, iso channel number 10 is enabled. If bit 9 is set, iso channel number 9 is enabled. If bit 8 is set, iso channel number 8 is enabled. If bit 7 is set, iso channel number 7 is enabled. If bit 6 is set, iso channel number 6 is enabled. If bit 5 is set, iso channel number 5 is enabled. If bit 4 is set, iso channel number 4 is enabled. If bit 3 is set, iso channel number 3 is enabled. If bit 2 is set, iso channel number 2 is enabled. If bit 1 is set, iso channel number 1 is enabled. If bit 0 is set, iso channel number 0 is enabled.
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Interrupt Event Register
The interrupt event set/clear register reflects the state of the various FW323 interrupt sources. The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. This register is fully compliant with OHCI and the FW323 adds OHCI 1.0 compliant vendor-specific interrupt function to bit 30. When reading the interrupt event register, the return value is the bit-wise AND function of the interrupt event and interrupt mask registers per the 1394 Open Host Controller Interface Specification. Table 74. Interrupt Event Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Reserved vendorSpecific Reserved Type R RSC R R R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU R RSCU RSCU R R R R R R RSCU RSCU RU RU RSCU RSCU RSCU RSCU RSCU RSCU Default 0 X 0 0 0 X X X X X X X X 0 X X 0 0 0 0 0 0 X X X X X X X X X X
phyRegRcvd cycleToolLong unrecoverableError cycleInconsistent cycleLost cycle64Seconds cycleSynch phy Reserved busReset selfIDcomplete Reserved
lockRespErr postedWriteErr isochRx isochTx RSPkt RQPkt ARRS ARRQ respTxComplete reqTxComplete
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Internal Registers (continued)
Register: Type: Offset: Interrupt event register Read/set/clear/update 80h set register 84h clear register (returns the content of the interrupt event and interrupt mask registers when read) XXXX 0XXXh
Default:
Table 75. Interrupt Event Register Description Bit 31 30 29:27 26 25 Field Name Reserved vendorSpecific Reserved phyRegRcvd cycleTooLong Type R RSC R RSCU RSCU Description Reserved. Bit 31 returns 0 when read. This vendor-specific interrupt event is reported when serial ROM read is complete. Reserved. Bits 29:27 return 0s when read. The FW323 has received a PHY core register data byte which can be read from the PHY core layer control register. If bit 21 (cycleMaster) of the link control register is set, then this indicates that over 125 ms have elapsed between the start of sending a cycle start packet and the end of a subaction gap. The link control register bit 21 (cycleMaster) is cleared by this event. This event occurs when the FW323 encounters any error that forces it to stop operations on any or all of its subunits, for example, when a DMA context sets its dead bit. While this bit is set, all normal interrupts for the context(s) that caused this interrupt are blocked from being set. A cycle start was received that had values for cycleSeconds and cycleCount fields that are different from the values in bits 31:25 (cycleSeconds field) and bits 24:12 (cycleCount field) of the isochronous cycle timer register. A lost cycle is indicated when no cycle_start packet is sent/ received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start. This bit may be set either when it occurs or when logic predicts that it will occur. Indicates that the seventh bit of the cycle second counter has changed. Indicates that a new isochronous cycle has started. This bit is set when the low order bit of the cycle count toggles. Indicates the PHY core requests an interrupt through a status transfer. Reserved. Bit 18 returns 0 when read. Indicates that the PHY core chip has entered bus reset mode. A selfID Packet Stream Has Been Received. It is generated at the end of the bus initialization process. This bit is turned off simultaneously when bit 17 (busReset) is turned on.
24
unrecoverableError
RSCU
23
cycleInconsistent
RSCU
22
cycleLost
RSCU
21 20 19 18 17 16
cycle64Seconds cycleSynch PHY Reserved busReset selfIDcomplete
RSCU RSCU RSCU R RSCU RSCU
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Internal Registers (continued)
Table 75. Interrupt Event Register Description (continued) Bit 15:10 9 8 Field Name Reserved lockRespErr postedWriteErr Type RU RU RSCU Description Reserved. Bits 15:10 return 0s when read. Indicates that the FW323 sent a lock response for a lock request to a serial bus register, but did not receive an ack_complete. Indicates that a host bus error occurred while the FW323 was trying to write a 1394 write request, which had already been given an ack_complete, into system memory. Isochronous Receive DMA Interrupt. Indicates that one or more isochronous receive contexts have generated an interrupt. This is not a latched event; it is the ORing of all bits in the isochronous receive interrupt event and isochronous receive interrupt mask registers. The isochronous receive interrupt event register indicates which contexts have interrupted. Isochronous Transmit DMA Interrupt. Indicates that one or more isochronous transmit contexts have generated an interrupt. This is not a latched event; it is the ORing of all bits in the isochronous transmit interrupt event and isochronous transmit interrupt mask registers. The isochronous transmit interrupt event register indicates which contexts have interrupted. Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor's xferStatus and resCount fields have been updated. Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor's xferStatus and resCount fields have been updated. Asynchronous Receive Response DMA Interrupt. This bit is conditionally set upon completion of an ARRS DMA context command descriptor. Asynchronous Receive Request DMA Interrupt. This bit is conditionally set upon completion of an ARRQ DMA context command descriptor. Asynchronous Response Transmit DMA Interrupt. This bit is conditionally set upon completion of an ATRS DMA command. Asynchronous Request Transmit DMA Interrupt. This bit is conditionally set upon completion of an ATRQ DMA command.
7
isochRx
RSCU
6
isochTx
RSCU
5
RSPkt
RSCU
4
RQPkt
RSCU
3
ARRS
RSCU
2
ARRQ
RSCU
1 0
respTxComplete reqTxComplete
RSCU RSCU
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Internal Registers (continued)
Interrupt Mask Register
The interrupt mask set/clear register is used to enable the various FW323 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31), the enables for each interrupt event align with the interrupt event register bits (see Tables 74 and 75). This register is fully compliant with OHCI and the FW323 adds an OHCI 1.0 compliant interrupt function to bit 30. Table 76. Interrupt Mask Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Field Name masterIntEnable vendorSpecific Reserved Type R RSC R R R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU R RSCU RSCU R R R R R R RSCU RSCU RU RU RSCU RSCU RSCU RSCU RSCU RSCU Default 0 X 0 0 0 X X X X X X X X 0 X X 0 0 0 0 0 0 X X X X X X X X X X
phyRegRcvd cycleToolLong unrecoverableError cycleInconsistent cycleLost cycle64Seconds cycleSynch PHY core Reserved busReset selfIDcomplete Reserved
lockRespErr postedWriteErr isochRx isochTx RSPkt RQPkt ARRS ARRQ respTxComplete reqTxComplete
Interrupt mask register Read/set/clear/update 88h set register 8Ch clear register Default: XXXX 0XXXh Agere Systems Inc.
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Internal Registers (continued)
Table 77. Interrupt Mask Register Description Bit 31 Field Name masterIntEnable Type RSCU Description
30
vendorSpecific
29:0
Master Interrupt Enable. If this bit is set, then external interrupts are generated in accordance with the interrupt mask register. If this bit is cleared, then external interrupts are not generated, regardless of the interrupt mask register settings. RSC When this bit is set, this vendor-specific interrupt mask enables interrupt generation when bit 30 (vendorSpecific) of the interrupt event register is set. Same as Table 74, interrupt event register.
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Internal Registers (continued)
Isochronous Transmit Interrupt Event Register
The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST command completes and its interrupt bits are set. Upon determining that the interrupt event register isochTx (bit 6) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register. Table 78. Isochronous Transmit Interrupt Event Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X
isoXmit7 isoXmit6 isoXmit5 isoXmit4 isoXmit3 isoXmit2 isoXmi1t isoXmit0
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Internal Registers (continued)
Register: Type: Offset: Default: Isochronous transmit interrupt event register Read/set/clear 90h set register 94h clear register (returns IsoXmitEvent and IsoXmitMask when read) 0000 00XXh
Table 79. Isochronous Transmit Interrupt Event Register Description Bit 31:8 7 6 5 4 3 2 1 0 Field Name Reserved isoXmit7 isoXmit6 isoXmit5 isoXmit4 isoXmit3 isoXmit2 isoXmit1 isoXmit0 Type Description
R Reserved. Bits 31:8 return 0s when read. RSCU Isochronous transmit channel 7 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 6 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 5 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 4 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 3 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 2 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 1 caused the interrupt event register bit 6 (isochTx) interrupt. RSCU Isochronous transmit channel 0 caused the interrupt event register bit 6 (isochTx) interrupt.
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Internal Registers (continued)
Isochronous Transmit Interrupt Mask Register
The isochronous transmit interrupt mask set/clear register is used to enable the isochTx interrupt source on a perchannel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with the event register bits detailed in Table 81 and Table 82. Table 80. Isochronous Transmit Interrupt Mask Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X
isoXmit7 isoXmit6 isoXmit5 isoXmit4 isoXmit3 isoXmit2 isoXmi1t isoXmit0
Register: Type: Offset: Default:
Isochronous transmit interrupt mask register Read/set/clear 98h set register 9Ch clear register (returns IsoXmitEvent and IsoXmitMask when read) 0000 00XXh 93
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Isochronous Receive Interrupt Event Register
The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set. Upon determining that the interrupt event register isochRx (bit 7) interrupt has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the clear register Table 81. Isochronous Receive Interrupt Event Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
isoRecv7 isoRecv6 isoRecv5 isoRecv4 isoRecv3 isoRecv2 isoRecv1 isoRecv0
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Internal Registers (continued)
Register: Type: Offset: Default: Isochronous receive interrupt event register Read/set/clear/update A0h set register A4h clear register 0000 0000h
Table 82. Isochronous Receive Interrupt Event Description Bit 31:8 7 6 5 4 3 2 1 0 Field Name Reserved isoRecv7 isoRecv6 isoRecv5 isoRecv4 isoRecv3 isoRecv2 isoRecv1 isoRecv0 Type R RSCU RSCU RSCU RSCU RSCU RSCU RSCU RSCU Description Reserved. Bits 31:8 return 0s when read. Isochronous receive context 7 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 6 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 5 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 4 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 3 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 2 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 1 caused the interrupt event register bit 7 (isochRx) interrupt. Isochronous receive context 0 caused the interrupt event register bit 7 (isochRx) interrupt.
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Internal Registers (continued)
Isochronous Receive Interrupt Mask Register
The isochronous receive interrupt mask set/clear register is used to enable the isochRx interrupt source on a perchannel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases, the enables for each interrupt event align with the event register bits. Table 83. Isochronous Receive Interrupt Mask Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: 96 Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
isoRecv7 isoRecv6 isoRecv5 isoRecv4 isoRecv3 isoRecv2 isoRecv1 isoRecv0
Isochronous receive interrupt mask register Read/set/clear A8h set register ACh clear register 0000 000Xh Agere Systems Inc.
Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Registers (continued)
Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. Table 84. Fairness Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pri_req
Fairness control register Read only DCh 0000 0000h
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Internal Registers (continued)
Table 85. Fairness Control Register Description Bit 31:8 7:0 Field Name Type Reserved pri_req R RW Description Reserved. Bits 31:8 return 0s when read. This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY core during fairness interval.
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Internal Registers (continued)
Link Control Register
The link control register provides flags to enable and configure the link core cycle timer and receiver portions of the FW323. Table 86. Link Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name Reserved Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cycleSource cycleMaster CycleTimerEnable Reserved
RcvPhyPkt RcvSelfID Reserved
Link control register Read/set/clear/update E0h set register E4h clear register 00X0 0X00h
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Table 87. Link Control Register Description Bit 31:23 22 21 Field Name Reserved cycleSource cycleMaster Type R RSC RSCU Description Reserved. Bits 31:23 return 0s when read. Set to 0, since the FW323 does not support an external cycle timer. When this bit is set, and the PHY core has notified the FW323 that it is root, the FW323 generates a cycle start packet every time the cycle timer rolls over, based on the setting of bit 22. When this bit is cleared, the OHCI accepts received cycle start packets to maintain synchronization with the node which is sending them. This bit is automatically reset when bit 25 (cycleTooLong) of the interrupt event register is set and cannot be set until bit 25 (cycleTooLong) is cleared. When this bit is set, the cycle timer offset counts cycles of the 24.576 MHz clock and rolls over at the appropriate time based on the settings of the above bits. When this bit is cleared, the cycle timer offset does not count. Reserved. Bits 19:11 return 0s when read. When this bit is set, the receiver accepts incoming PHY core packets into the AR request context if the AR request context is enabled. This does not control receipt of self-identification. When this bit is set, the receiver accepts incoming self-identification packets. Before setting this bit to 1, software must ensure that the self-ID buffer pointer register contains a valid address. Reserved. Bits 8:0 return 0s when read.
20
CycleTimerEnable
RSC
19:11 10
Reserved RcvPhyPkt
R RSC
9
RcvSelfID
RSC
8:0
Reserved
R
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Internal Registers (continued)
Node Identification Register
The node identification register contains the address of the node on which the OHCI resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15:6) and the NodeNumber field (bits 5:0) is referred to as the node ID. Table 88. Node Identification Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name IDValid root Reserved CPS Reserved Type RU RU R R RU R R R R R R R R R R R RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
busNumber
NodeNumber
Node identification register Read/write/update E8h 0000 FFXXh
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Internal Registers (continued)
Table 89. Node Identification Register Description Bit 31 Field Name iDValid Type RU Description
30 29:28 27 26:16 15:6 5:0
This bit indicates whether or not the FW323 has a valid node number. It is cleared when a 1394 bus reset is detected and set when the FW323 receives a new node number from the PHY core. root RU This bit is set during the bus reset process if the attached PHY core is root. Reserved R Reserved. Bits 29:28 return 0s when read. CPS RU Set if the PHY core is reporting that cable power status is OK. Reserved R Reserved. Bits 26:16 return 0s when read. busNumber RWU This number is used to identify the specific 1394 bus to which the FW323 belongs when multiple 1394-compatible buses are connected via a bridge. NodeNumber RU This number is the physical node number established by the PHY core during self-identification. It is automatically set to the value received from the PHY core after the self-identification phase. If the PHY core sets the nodeNumber to 63, then software should not set ContextControl.run for either of the AT DMA contexts.
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Internal Registers (continued)
PHY Core Layer Control Register
The PHY core layer control register is used to read or write a PHY core register. Table 90. PHY Core Layer Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name rdDone Reserved Type RU R R R RU RU RU RU RU RU RU RU RU RU RU RU RWU RWU R R RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rdAddr
rdData
rdReg wrReg Reserved regAddr
wrData
PHY core layer control register Read/write/update ECh 0000 0000h
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Internal Registers (continued)
Table 91. PHY Core Layer Control Register Description Bit 31 30:28 27:24 23:16 15 Field Name rdDone Reserved rdAddr rdData rdReg Type RU Description
14
wrReg
13:12 11:8 7:0
Reserved regAddr wrData
This bit is cleared to 0 by the FW323 when either bit 15 (rdReg) or bit 14 (wrReg) is set. This bit is set when a register transfer is received from the PHY core. R Reserved. Bits 30:28 return 0s when read. RU This is the address of the register most recently received from the PHY core. RU This field is the contents of a PHY core register which has been read. RWU This bit is set by software to initiate a read request to a PHY core register and is cleared by hardware when the request has been sent. Bit 14 (wrReg) and bit 15 (rdReg) must be used exclusively. RWU This bit is set by software to initiate a write request to a PHY core register and is cleared by hardware when the request has been sent. Bit 14 (wrReg) and bit 15 (rdReg) must be used exclusively. R Reserved. Bits 13:12 return 0s when read. RW This field is the address of the PHY core register to be written or read. RW This field is the data to be written to a PHY core register and is ignored for reads.
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Internal Registers (continued)
Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the FW323 is cycle master, this register is transmitted with the cycle start message. When the FW323 is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference. Table 92. Isochronous Cycle Timer Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name cycleSeconds Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cycleCount
cycleOffset
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Internal Registers (continued)
Register: Type: Offset: Default: Isochronous cycle timer register Read/write/update F0h XXXX XXXXh
Table 93. Isochronous Cycle Timer Register Description Bit 31:25 24:12 11:0 Field Name cycleSeconds cycleCount cycleOffset Type Description
RWU This field counts seconds [rollovers from bits 24:12 (cycleCount field)] modulo 128. RWU This field counts cycles [rollovers from bits 11:0 (cycleOffset field)] modulo 8000. RWU This field counts 24.576 MHz clocks modulo 3072, i.e., 125 ms. If an external 8 kHz clock configuration is being used, then this bit must be set to 0 at each tick of the external clock.
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Internal Registers (continued)
Asynchronous Request Filter High Register
The asynchronous request filter high set/clear register is used to enable asynchronous receive requests on a pernode basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set in this register, then the packet is not acknowledged and the request is not queued. The node ID comparison is done if the source node is on the same bus as the FW323. All nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set. Table 94. Asychronous Request Filter High Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name asynReqAllBuses asynReqResource62 asynReqResource61 asynReqResource60 asynReqResource59 asynReqResource58 asynReqResource57 asynReqResource56 asynReqResource55 asynReqResource54 asynReqResource53 asynReqResource52 asynReqResource51 asynReqResource50 asynReqResource49 asynReqResource48 asynReqResource47 asynReqResource46 asynReqResource45 asynReqResource44 asynReqResource43 asynReqResource42 asynReqResource41 asynReqResource40 asynReqResource39 asynReqResource38 asynReqResource37 asynReqResource36 asynReqResource35 asynReqResource34 asynReqResource33 asynReqResource32 Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Internal Registers (continued)
Register: Type: Offset: Default: Asynchronous request filter high register Read/set/clear 100h set register 104h clear register 0000 0000h
Table 95. Asynchronous Request Filter High Register Description Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 Field Name asynReqAllBuses asynReqResource62 asynReqResource61 asynReqResource60 asynReqResource59 asynReqResource58 asynReqResource57 asynReqResource56 asynReqResource55 asynReqResource54 asynReqResource53 asynReqResource52 asynReqResource51 asynReqResource50 asynReqResource49 asynReqResource48 asynReqResource47 asynReqResource46 asynReqResource45 Type Description
RSC If this bit is set, then all asynchronous requests received by the FW323 from nonlocal bus nodes are accepted. RSC If this bit is set, then asynchronous requests received from node 62 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 61 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 60 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 59 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 58 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 57 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 56 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 55 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 54 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 53 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 52 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 51 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 50 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 49 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 48 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 47 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 46 on local bus are accepted by FW323. RSC If this bit is set, then asynchronous requests received from node 45 on local bus are accepted by FW323.
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Internal Registers (continued)
Table 95. Asynchronous Request Filter High Register Description (continued) Bit 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Type Description requests received from node 44 on local requests received from node 43 on local requests received from node 42 on local requests received from node 41 on local requests received from node 40 on local requests received from node 39 on local requests received from node 38 on local requests received from node 37 on local requests received from node 36 on local requests received from node 35 on local requests received from node 34 on local requests received from node 33 on local requests received from node 32 on local
asynReqResource44 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource43 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource42 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource41 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource40 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource39 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource38 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource37 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource36 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource35 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource34 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource33 RSC If this bit is set, then asynchronous bus are accepted by FW323. asynReqResource32 RSC If this bit is set, then asynchronous bus are accepted by FW323.
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Internal Registers (continued)
Asynchronous Request Filter Low Register
The asynchronous request filter low set/clear register is used to enable asynchronous receive requests on a pernode basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. Table 96. Asynchronous Request Filter Low Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: 110 Field Name asynReqResource31 asynReqResource30 asynReqResource29 asynReqResource28 asynReqResource27 asynReqResource26 asynReqResource25 asynReqResource24 asynReqResource23 asynReqResource22 asynReqResource21 asynReqResource20 asynReqResource19 asynReqResource18 asynReqResource17 asynReqResource16 asynReqResource15 asynReqResource14 asynReqResource13 asynReqResource12 asynReqResource11 asynReqResource10 asynReqResource9 asynReqResource8 asynReqResource7 asynReqResource6 asynReqResource5 asynReqResource4 asynReqResource3 asynReqResource2 asynReqResource1 asynReqResource0 Asynchronous request filter low register Read/set/clear 108h set register 10Ch clear register 0000 0000h Agere Systems Inc. Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Internal Registers (continued)
Table 97. Asynchronous Request Filter Low Register Description Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Field Name Type Description
asynReqResource31 RSC If this bit is set for local bus node number 31, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource30 RSC If this bit is set for local bus node number 30, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource29 RSC If this bit is set for local bus node number 29, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource28 RSC If this bit is set for local bus node number 28, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource27 RSC If this bit is set for local bus node number 27, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource26 RSC If this bit is set for local bus node number 26, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource25 RSC If this bit is set for local bus node number 25, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource24 RSC If this bit is set for local bus node number 24, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource23 RSC If this bit is set for local bus node number 23, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource22 RSC If this bit is set for local bus node number 22, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource21 RSC If this bit is set for local bus node number 21, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource20 RSC If this bit is set for local bus node number 20, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource19 RSC If this bit is set for local bus node number 19, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource18 RSC If this bit is set for local bus node number 18, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource17 RSC If this bit is set for local bus node number 17, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource16 RSC If this bit is set for local bus node number 16, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource15 RSC If this bit is set for local bus node number 15, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource14 RSC If this bit is set for local bus node number 14, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource13 RSC If this bit is set for local bus node number 13, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource12 RSC If this bit is set for local bus node number 12, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource11 RSC If this bit is set for local bus node number 11, then asynchronous requests received by the FW323 from that node are accepted. asynReqResource10 RSC If this bit is set for local bus node number 10, then asynchronous requests received by the FW323 from that node are accepted.
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Internal Registers (continued)
Table 97. Asynchronous Request Filter Low Register Description (continued) Bit 9 8 7 6 5 4 3 2 1 0 Field Name asynReqResource9 asynReqResource19 asynReqResource18 asynReqResource17 asynReqResource16 asynReqResource15 asynReqResource14 asynReqResource13 asynReqResource12 asynReqResource11 Type Description
RSC If this bit is set for local bus node number 9, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 8, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 7, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 6, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 5, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 4, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 3, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 2, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 1, then asynchronous requests received by the FW323 from that node are accepted. RSC If this bit is set for local bus node number 0, then asynchronous requests received by the FW323 from that node are accepted.
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Internal Registers (continued)
Physical Request Filter High Register
The physical request filter high set/clear register is used to enable physical receive requests on a per-node basis and handle the upper node IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the ARRQ context instead of the physical request context. Table 98. Physical Request Filter High Register
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name physReqAllBuses physReqResource62 physReqResource61 physReqResource60 physReqResource59 physReqResource58 physReqResource57 physReqResource56 physReqResource55 physReqResource54 physReqResource53 physReqResource52 physReqResource51 physReqResource50 physReqResource49 physReqResource48 physReqResource47 physReqResource46 physReqResource45 physReqResource44 physReqResource43 physReqResource42 physReqResource41 physReqResource40 physReqResource39 physReqResource38 physReqResource37 physReqResource36 physReqResource35 physReqResource34 physReqResource33 physReqResource32 Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Type: Offset: Default:
Physical request filter high register Read/set/clear 100h set register 104h clear register 0000 0000h 113
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Internal Registers (continued)
Table 99. Physical Request Filter High Register Description Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Field Name physReqAllBuses physReqResource62 physReqResource61 physReqResource60 physReqResource59 physReqResource58 physReqResource57 physReqResource56 physReqResource55 physReqResource54 physReqResource53 physReqResource52 physReqResource51 physReqResource50 physReqResource49 physReqResource48 physReqResource47 physReqResource46 physReqResource45 physReqResource44 physReqResource43 physReqResource42 Type Description
RSC If this bit is set, then all asychronous requests received by the FW323 from nonlocal bus nodes are accepted. RSC If this bit is set, requests received by the FW323 from local bus node 62 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 61 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 60 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 59 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 58 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 57 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 56 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 55 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 54 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 53 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 52 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 51 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 50 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 49 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 48 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 47 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 46 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 45 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 44 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 43 will be handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus node 42 will be handled through the physical request context.
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Internal Registers (continued)
Table 99. Physical Request Filter High Register Description (continued) Bit 9 8 7 6 5 4 3 2 1 0 Field Name Type Description
physReqResource41 RSC If this bit is set, requests received by the FW323 from local bus node 41 will be handled through the physical request context. physReqResource40 RSC If this bit is set, requests received by the FW323 from local bus node 40 will be handled through the physical request context. physReqResource41 RSC If this bit is set, requests received by the FW323 from local bus node 39 will be handled through the physical request context. physReqResource40 RSC If this bit is set, requests received by the FW323 from local bus node 38 will be handled through the physical request context. physReqResource37 RSC If this bit is set, requests received by the FW323 from local bus node 37 will be handled through the physical request context. physReqResource36 RSC If this bit is set, requests received by the FW323 from local bus node 36 will be handled through the physical request context. physReqResource35 RSC If this bit is set, requests received by the FW323 from local bus node 35 will be handled through the physical request context. physReqResource34 RSC If this bit is set, requests received by the FW323 from local bus node 34 will be handled through the physical request context. physReqResource33 RSC If this bit is set, requests received by the FW323 from local bus node 33 will be handled through the physical request context. physReqResource32 RSC If this bit is set, requests received by the FW323 from local bus node 32 will be handled through the physical request context.
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Internal Registers (continued)
Physical Request Filter Low Register
The physical request filter low set/clear register is used to enable physical receive requests on a per-node basis and handle the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register. If the bit corresponding to the node ID is not set in this register, then the request is handled by the asynchronous request context instead of the physical request context. Table 100. Physical Request Filter Low Register Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field Name
physReqResource31 physReqResource30 physReqResource29 physReqResource28 physReqResource27 physReqResource26 physReqResource25 physReqResource24 physReqResource23 physReqResource22 physReqResource21 physReqResource20 physReqResource19 physReqResource18 physReqResource17 physReqResource16 physReqResource15 physReqResource14 physReqResource13 physReqResource12 physReqResource11 physReqResource10 physReqResource9 physReqResource8 physReqResource7 physReqResource6 physReqResource5 physReqResource4 physReqResource3 physReqResource2 physReqResource1 physReqResource0
Type
RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC
Default
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Type: Offset: Default: 116
Physical request filter low register Read/set/clear 108h set register 11Ch clear register 0000 0000h Agere Systems Inc.
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Internal Registers (continued)
Table 101. Physical Request Filter Low Register Description Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Field Name Type Description
physReqResource31 RSC If this bit is set, requests received by the FW323 from local bus node 31 will be handled through the physical request context. physReqResource30 RSC If this bit is set, requests received by the FW323 from local bus node 30 will be handled through the physical request context. physReqResource29 RSC If this bit is set, requests received by the FW323 from local bus node 29 will be handled through the physical request context. physReqResource28 RSC If this bit is set, requests received by the FW323 from local bus node 28 will be handled through the physical request context. physReqResource27 RSC If this bit is set, requests received by the FW323 from local bus node 27 will be handled through the physical request context. physReqResource26 RSC If this bit is set, requests received by the FW323 from local bus node 26 will be handled through the physical request context. physReqResource25 RSC If this bit is set, requests received by the FW323 from local bus node 25 will be handled through the physical request context. physReqResource24 RSC If this bit is set, requests received by the FW323 from local bus node 24 will be handled through the physical request context. physReqResource23 RSC If this bit is set, requests received by the FW323 from local bus node 23 will be handled through the physical request context. physReqResource22 RSC If this bit is set, requests received by the FW323 from local bus node 22 will be handled through the physical request context. physReqResource21 RSC If this bit is set, requests received by the FW323 from local bus node 21 will be handled through the physical request context. physReqResource20 RSC If this bit is set, requests received by the FW323 from local bus node 20 will be handled through the physical request context. physReqResource19 RSC If this bit is set, requests received by the FW323 from local bus node 19 will be handled through the physical request context. physReqResource18 RSC If this bit is set, requests received by the FW323 from local bus node 18 will be handled through the physical request context. physReqResource17 RSC If this bit is set, requests received by the FW323 from local bus node 17 will be handled through the physical request context. physReqResource16 RSC If this bit is set, requests received by the FW323 from local bus node 16 will be handled through the physical request context. physReqResource15 RSC If this bit is set, requests received by the FW323 from local bus node 15 will be handled through the physical request context. physReqResource14 RSC If this bit is set, requests received by the FW323 from local bus node 14 will be handled through the physical request context. physReqResource13 RSC If this bit is set, requests received by the FW323 from local bus node 13 will be handled through the physical request context. physReqResource12 RSC If this bit is set, requests received by the FW323 from local bus node 12 will be handled through the physical request context. physReqResource11 RSC If this bit is set, requests received by the FW323 from local bus node 11 will be handled through the physical request context. physReqResource10 RSC If this bit is set, requests received by the FW323 from local bus node 10 will be handled through the physical request context.
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Internal Registers (continued)
Table 101. Physical Request Filter Low Register Description (continued) Bit 9 8 7 6 5 4 3 2 1 0 Field Name physReqResource9 physReqResource8 physReqResource7 physReqResource6 physReqResource5 physReqResource4 physReqResource3 physReqResource2 physReqResource1 physReqResource0 Type Description node 9 will be node 8 will be node 7 will be node 6 will be node 5 will be node 4 will be node 3 will be node 2 will be node 1 will be node 0 will be
RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context. RSC If this bit is set, requests received by the FW323 from local bus handled through the physical request context.
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Internal Registers (continued)
Asynchronous Context Control Register
The asynchronous context control set/clear register controls the state and indicates status of the DMA context. Table 102. Asynchronous Context Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name Reserved Type R R R R R R R R R R R R R R R R RSCU R R RSU RU RU R R RU RU RU RU RU RU RU RU Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 X X X X X X X X
run Reserved wake dead active Reserved spd
eventcode
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Internal Registers (continued)
Register: Type: Offset: Asynchronous context control register Read/set/clear/update 180h set register (ATRQ) 184h clear register (ATRQ) 1A0h set register (ATRS) 1A4h clear register (ATRS) 1C0h set register (ARRQ) 1C4h clear register (ARRQ) 1E0h set register (ATRS) 1E4h clear register (ATRS) 0000 X0XXh
Default:
Table 103. Asynchronous Context Control Register Description Bit 31:16 15 Field Name Reserved run Type R RSCU Description Reserved. Bits 31:16 return 0s when read. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The FW323 changes this bit only on a hardware or software reset. Reserved. Bits 14:13 return 0s when read. Software sets this bit to cause the FW323 to continue or resume descriptor processing. The FW323 clears this bit on every descriptor fetch. The FW323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). The FW323 sets this bit to 1 when it is processing descriptors. Reserved. Bits 9:8 return 0s when read. This field indicates the speed at which a packet was received or transmitted, and only contains meaningful information for receive contexts. This field is encoded as: 000 = 100 Mbits/s. 001 = 200 Mbits/s. 010 = 400 Mbits/s, and all other values are reserved. This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully.
14:13 12
Reserved wake
R RSU
11 10 9:8 7:5
dead active Reserved spd
RU RU R RU
4:0
eventcode
RU
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Internal Registers (continued)
Asynchronous Context Command Pointer Register
The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables the context by setting the asynchronous context control register bit 15 (run). Table 104. Asynchronous Context Command Pointer Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Name descriptorAddress Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Z
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Internal Registers (continued)
Register: Type: Offset: Asynchronous context command pointer register Read/write/update 19Ch (ATRQ) 1ACh (ATRS) 1CCh (ATRQ) 1ECh (ATRS) XXXX XXXXh
Default:
Table 105. Asynchronous Context Command Pointer Register Description Bit 31:4 3:0 Field Name descriptorAddress Z Type RWU RWU Description Contains the upper 28 bits of the address of a 16-byte aligned descriptor block. Indicates the number of contiguous descriptors at the address pointed to by the descriptor address. If Z is 0, then it indicates that the descriptorAddress field (bits 31:4) is not valid.
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Internal Registers (continued)
Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7). Table 106. Isochronous Transmit Context Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name cycleMatchEnable cycleMatch Type RSCU RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC R R RSU RU RU R R RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X 0 0 0 X 0 0 0 0 X X X X X X X X
run Reserved wake dead active Reserved spd
event code
Isochronous transmit context control register Read/set/clear/update 200h + (16 * n) set register 204h + (16 * n) clear register XXXX X0XXh
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Internal Registers (continued)
Table 107. Isochronous Transmit Context Control Register Description Bit 31 Field Name cycleMatchEnable Type RSCU Description When this bit is set to 1, processing occurs such that the packet described by the context's first descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field (bits 30:16). The cycleMatch field (bits 30:16) must match the low-order 2 bits of cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead, the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted. The effects of this bit, however, are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification. Once the context has become active, hardware clears this bit. Contains a 15-bit value, corresponding to the low-order 2 bits of the bus isochronous cycle timer register cycleSeconds field (bits 31: 25) and the cycleCount field (bits 24:12). If bit 31 (cycleMatchEnable) is set, then this isochronous transmit DMA context becomes enabled for transmits when the low-order 2 bits of the bus isochronous cycle timer register cycleSeconds field (bits 31:25) and the cycleCount field (bits 24:12) value equal this field's (cycleMatch) value. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The FW323 changes this bit only on a hardware or software reset. Reserved. Bits 14:13 return 0s when read. Software sets this bit to cause the FW323 to continue or resume descriptor processing. The FW323 clears this bit on every descriptor fetch. The FW323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). The FW323 sets this bit to 1 when it is processing descriptors. Reserved. Bits 9:5 return 0s when read. Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
30:16
cycleMatch
RSC
15
run
RSC
14:13 12
Reserved wake
R RSU
11 10 9:5 4:0
dead active Reserved event code
RU RU R RU
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Internal Registers (continued)
Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7). Table 108. Isochronous Transmit Context Command Pointer Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name descriptorAddress Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Isochronous transmit context command pointer register Read only 20Ch + (16 * n) XXXX XXXXh 125
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Internal Registers (continued)
Table 109. Isochronous Transmit Context Command Pointer Register Description Bit 31:0 Field Name descriptorAddress Type R Description Address of the context program which will be executed when a DMA context is started.
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Internal Registers (continued)
Isochronous Receive Context Control Register
The isochronous receive context control set/clear register controls options, state, and status for the isochronous receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0:7). Table 110. Isochronous Receive Context Control Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name bufferFill isochHeader cycleMatchEnable multiChanMode Reserved Type RSC RSC RSCU RSC R R R R R R R R R R R R RSCU R R RSU RU RU R R RU RU RU RU RU RU RU RU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
run Reserved wake dead active Reserved spd
event code
Isochronous receive context control register Read/set/clear/update 400h + (32 * n) set register 404h + (32 *n) clear register X000 X0XXh
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Table 111. Isochronous Receive Context Control Register Description Bit 31 Field Name bufferFill Type RSC Description When this bit is set, received packets are placed back-to-back to completely fill each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1, then this bit must also be set to 1. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. When this bit is 1, received isochronous packets include the complete 4-byte isochronous packet header seen by the link layer. The end of the packet is marked with an xferStatus in the first doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart packet. When this bit is cleared, the packet header is stripped off of received isochronous packets. The packet header, if received, immediately precedes the packet payload. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. When this bit is set, the context begins running only when the 13-bit cycleMatch field (bits 24:12) in the isochronous receive context match register matches the 13-bit cycleCount field in the cycleStart packet. The effects of this bit, however, are impacted by the values of other bits in this register. Once the context has become active, hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set. When this bit is set, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high and isochronous receive channel mask low registers. The isochronous channel number specified in the isochronous receive DMA context match register is ignored. When this bit is cleared, the isochronous receive DMA context receives packets for the channel number specified in the context match register. Only one isochronous receive DMA context may use the isochronous receive channel mask registers. If more that one isochronous receive context control register has this bit set, then results are undefined. The value of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1. Reserved. Bits 27:16 return 0s when read. This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing. The FW323 changes this bit only on a hardware or software reset. Reserved. Bits 14:13 return 0s when read. Software sets this bit to cause the FW323 to continue or resume descriptor processing. The FW323 clears this bit on every descriptor fetch. The FW323 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 (run). The FW323 sets this bit to 1 when it is processing descriptors. Reserved. Bits 9:8 return 0s when read. This field indicates the speed at which the packet was received. 000 = 100 Mbits/s. 001 = 200 Mbits/s. 010 = 400 Mbits/s. All other values are reserved. Following an INPUT_* command, the error or status code is indicated in this field. Agere Systems Inc.
30
isochHeader
RSC
29
cycleMatchEnable
RSCU
28
multiChanMode
RSC
27:16 15
Reserved run
R RSCU
14:13 12 11 10 9:8 7:5
Reserved wake dead active Reserved spd
R RSU RU RU R RU
4:0
event code
RU
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Internal Registers (continued)
Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the FW323 accesses when software enables an isochronous receive context by setting the isochronous receive context control register bit 15 (run). The n value in the following register addresses indicates the context number (n = 0:7). Table 112. Isochronous Receive Context Command Pointer Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name descriptorAddress Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU Default X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Isochronous receive context command pointer register Read only 40Ch + (32 * n) XXXX XXXXh 129
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Table 113. Isochronous Receive Context Command Pointer Register Description Bit 31:0 Field Name descriptorAddress Type RWU Description Address of the context program which will be executed when a DMA context is started.
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Internal Registers (continued)
Isochronous Receive Context Match Register
The isochronous receive context match register is used to control on which isochronous cycle the context should start. The register is also used to control which packets are accepted by the context. Table 114. Isochronous Receive Context Match Register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register: Type: Offset: Default: Field Name tag3 tag2 tag1 tag0 Reserved Type RW RW RW RW R R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW Default X X X X 0 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X
cycleMatch
sync
Reserved tag1SyncFilter channelNumber
Isochronous receive context match register Read only 410Ch + (32 * n) XXXX XXXXh
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Table 115. Isochronous Receive Context Match Register Description Bit 31 30 29 28 27:25 24:12 Field Name tag3 tag2 tag1 tag0 Reserved cycleMatch Type RW RW RW RW R RW Description If this bit is set, then this context matches on iso receive packets with a tag field of 11b. If this bit is set, then this context matches on iso receive packets with a tag field of 10b. If this bit is set, then this context matches on iso receive packets with a tag field of 01b. If this bit is set, then this context matches on iso receive packets with a tag field of 00b. Reserved. Bits 27:25 return 0s when read. Contains a 15-bit value, corresponding to the low-order 2 bits of cycleSeconds and the 13-bit cycleCount field in the cycleStart packet. If isochronous receive context control register bit 29 (cycleMatchEnable) is set, then this context is enabled for receives when the 2 low-order bits of the bus isochronous cycle timer register cycleSeconds field (bits 31:25) and cycleCount field (bits 24:12) value equal this field's (cycleMatch) value. This field contains the 4-bit field which is compared to the sync field of each iso packet for this channel when the command descriptor's w field is set to 11b. Reserved. Bit 7 returns 0 when read. If this bit and bit 29 (tag1) are set, then packets with tag2b01 are accepted into the context if the two most significant bits of the packets sync field are 00b. Packets with tag values other than 01b are filtered according to tag0, tag2, and tag3 (bits 28, 30, and 31, respectively) without any additional restrictions. If this bit is cleared, then this context matches on isochronous receive packets as specified in bits 28:31 (tag0:tag3) with no additional restrictions. This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets.
11:8
sync
RW
7 6
Reserved tag1SyncFilter
R RW
5:0
channelNumber
RW
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Internal Registers (continued)
FW323 Vendor Specific Registers
The FW323 contains a number of vendor-defined registers used for diagnostics and control low-level hardware functions. These registers are addressable in the upper 2K of the 4K region defined by PCI base address register 0 (registers defined by the OHCI specification reside in the lower 2K of this region). The control registers should not be changed when the link is enabled. Table 116. FW323 Vendor Specific Registers Description Offset 12'h800 12'h808 Register Name IsoDMACtrl AsyDMACtrl Description Controls PCI access for the isochronous DMA contents. Initial values are loaded from serial EEPROM, if present. Controls PCI access and AT FIFO threshold for the asynchronous DMA contexts. Initial values are loaded from serial EEPROM, if present. Controls low level functionality of the link core. Initial values are loaded from serial EEPROM, if present.
12'h840
LinkOptions
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Isochronous DMA Control
The fields in this register control when the isochronous DMA engines access the PCI bus and how much data they will attempt to move in a single PCI transaction. The actual PCI burst sizes will also be affected by 1394 packet size, host memory buffer size, FIFO constraints, and the PCI cache line size. This register is accessible via the PCI bus at offset 0x800. Table 117. Isochronous DMA Control Registers Description Bits 15:12 Field Description
11:8
7:4
3:0
IT Maximum Burst The maximum number of quadlets that will be fetched by the IT unit in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets. Defaults to 7 (128 quadlets). IT Threshold Along with the amount of data remaining to be fetched from the current host memory buffer, this field defines the number of quadlets that must be unused in the IT FIFO before the IT unit will request access to the PCI bus. In effect, this value defines the minimum burst size that, other factors permitting, will be used in IT. The threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets). IR Maximum Burst The maximum number of quadlets that will be written by the IR unit in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets. Defaults to 7 (128 quadlets). IR Threshold Along with the space remaining in the current host memory buffer, this field defines the number of quadlets that must be available in the IR FIFO before the IR unit will request access to the PCI bus. The threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets).
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Internal Registers (continued)
Asynchronous DMA Control
This register is accessible via the PCI bus at offset 0x808. Table 118. Asynchronous DMA Control Registers Description Bits 23:16 Field Description
15:12
11:8
7:4
3:0
AT FIFO Threshold The number of quadlets of a packet that must be in the AT FIFO before the link will be notified that there is an asynchronous packet to be transmitted. (The link will also be signaled that a packet is available for transmission if the entire packet is in the FIFO, regardless of its size.) Defaults to a value of 0x10 (256 quadlets). AT Maximum Burst The maximum number of quadlets that will be fetched by the AT and physical read response units in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets. Defaults to 7 (128 quadlets). AT Threshold Along with the amount of data remaining to be fetched from the current host memory buffer, this field defines the number of quadlets that can be written to the AT FIFO before the AT and physical read response units will request access to the PCI bus. The threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets). AR Maximum Burst The maximum number of quadlets that will be written by the AR and physical write units in one PCI transaction. The maximum burst is 16 * (n + 1) quadlets. Defaults to 7 (128 quadlets). AR Threshold Along with the space remaining in the current host memory buffer, this field defines the number of quadlets that must be available in the AR FIFO before the AR unit will request access to the PCI bus. For the physical write unit, this value defines the minimum PCI burst, packet size permitting. The threshold is 16 * (n + 1) quadlets and defaults to 3 (64 quadlets).
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Data Sheet, Rev. 2 October 2001
Internal Registers (continued)
Link Options
The values in this register control the operation of the link module within the FW323 beyond what is stated in 1394 and OHCI specifications. In general, these controls are to be used for debugging and diagnostic purposes only and should not be modified from power reset default values. This register is accessible via the PCI bus at offset 0x840. Table 119. Link Registers Description Bits 5:3 Field Posted Wires Description Number of physical posted writes the link is allowed to queue in the asynchronous receive FIFO. Defaults to four, which is the maximum value. Values greater than four will disable all physical posted writes. Selects the value the FW323 will use for its isochronous cycle period when the FW323 is the root node. This value is for debugging purposes only and should not be set to other than it's default value in a real 1394 network. This value defaults to 0. If 0, cycle = 125 s. If 1, cycle = 62.5 s. If 2, cycle = 31.25 s. If 3, cycle = 15.625 s. If 4, cycle = 7.8125 s.
2:0
Cycle Timer Control
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Internal Registers (continued)
Table 120. ROM Format Description Byte Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 Description Subsystem Vendor ID, 1 s Byte Subsystem Vendor ID, ms Byte Subsystem ID, 1 s Byte Subsystem ID, ms Byte PCI Min Grant Value PCI Max Latency Value Reserved PCI Global Swap Control (bit 0) IsoDMACtrl[7:0] IsoDMACtrl[15:8] IsoDMACtrl[23:16] IsoDMACtrl[31:24] AsyDMACtrl[7:0] AsyDMACtrl[15:8] AsyDMACtrl[23:16] AsyDMACtrl[31:24] LinkOptions[7:0] LinkOptions[15:8] LinkOptions[23:16] LinkOptions[31:24] OHCI Bus Options[7:0] OHCI Bus Options[15:8] OHCI Bus Options[23:16] OHCI Bus Options[31:24] OHCI GUIDHi[7:0] OHCI GUIDHi[15:8] OHCI GUIDHi[23:16] OHCI GUIDHi[31:24] OHCI GUIDLo[7:0] OHCI GUIDLo[15:8] OHCI GUIDLo[23:16] OHCI GUIDLo[31:24] OHCI ConfigRomHdr[7:0] OHCI ConfigRomHdr[15:8] OHCI ConfigRomHdr[23:16] OHCI ConfigRomHdr[31:24] Start of System Defined Configuration Space
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Data Sheet, Rev. 2 October 2001
Crystal Selection Considerations
The FW323 is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. IEEE 1394a-2000 standard requires that FW323 have less than 100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this, it is recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used. The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm.
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant mode crystal circuits. Total load capacitance (CL) is a function of not only the discrete load capacitors, but also capacitances from the FW323 board traces and capacitances of the other FW323 connected components.The values for load capacitors (CA and CB) should be calculated using this formula: CA = CB = (CL - Cstray) x 2 Where: CL = load capacitance specified by the crystal manufacturer Cstray = capacitance of the board and the FW323, typically 2 pF--3 pF
Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing noise introduced into the FW323 PLL. The crystal and two-load capacitors should be considered as a unit during layout. They should be placed as close as possible to one another, while minimizing the loop area created by the combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possible to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the X1 and X0 signals.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 121. Absolute Maximum Ratings Parameter Supply Voltage Range Input Voltage Range* Output Voltage Range at Any Output Operating Free Air Temperature Storage Temperature Range Symbol VDD VI VO TA Tstg Min 3.0 -0.5 -0.5 0 -65 Max 3.6 VDD + 0.5 VDD + 0.5 70 150 Unit V V V C C
* Except for 5 V tolerant I/O (CTL0, CTL1, D0--D7, and LREQ), where VI max = 5.5 V.
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Data Sheet, Rev. 2 October 2001
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Electrical Characteristics
Table 122. Analog Characteristics Parameter Supply Voltage Differential Input Voltage Test Conditions Source power node Cable inputs, 100 Mbits/s operation Cable inputs, 200 Mbits/s operation Cable inputs, 400 Mbits/s operation Cable inputs, during arbitration TPB cable inputs, speed signaling off TPB cable inputs, S100 speed signaling on TPB cable inputs, S200 speed signaling on TPB cable inputs, S400 speed signaling on TPB cable inputs, speed signaling off TPB cable inputs, S100 speed signaling on TPB cable inputs, S200 speed signaling on TPB cable inputs, S400 speed signaling on TPA, TPB cable inputs, 100 Mbits/s operation TPA, TPB cable inputs, 200 Mbits/s operation TPA, TPB cable inputs, 400 Mbits/s operation Between TPA and TPB cable inputs, 100 Mbits/s operation Between TPA and TPB cable inputs, 200 Mbits/s operation Between TPA and TPB cable inputs, 400 Mbits/s operation -- Symbol VDD--SP VID--100 VID--200 VID--400 VID--ARB VCM VCM--SP--100 VCM--SP--200 VCM--SP--400 VCM VCM--NSP--100 VCM--NSP--200 VCM--NSP--400 -- -- -- -- -- -- VTH+ Min 3.0 142 132 100 168 1.165 1.165 0.935 0.532 1.165 1.165 0.935 0.532 -- -- -- -- -- -- 89 Typ 3.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 3.6 260 260 260 265 2.515 2.515 2.515 2.515 2.015 2.015 2.015 2.015 1.08 0.5 0.315 0.8 0.55 0.5 168 Unit V mV mV mV mV V V V V V V V V ns ns ns ns ns ns mV
Common-mode Voltage Source Power Mode
Common-mode Voltage Nonsource Power Mode*
Receive Input Jitter
Receive Input Skew
Positive Arbitration Comparator Input Threshold Voltage Negative Arbitration Comparator Input Threshold Voltage Speed Signal Input Threshold Voltage Output Current TPBIAS Output Voltage Current Source for Connect Detect Circuit
--
VTH-
-168
--
-89
mV
200 Mbits/s 400 Mbits/s TPBIAS outputs At rated I/O current --
VTH--S200 VTH--S400 IO VO ICD
45 266 -5 1.665 --
-- -- -- -- --
139 445 2.5 2.015 76
mV mV mA V A
* For a node that does not source power (see Section 4.2.2.2 in IEEE 1394-1995 Standard).
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Data Sheet, Rev. 2 October 2001
Electrical Characteristics (continued)
Table 123. Driver Characteristics Parameter Differential Output Voltage Off-state Common-mode Voltage Driver Differential Current, TPA+, TPA-, TPB+, TPB- Common-mode Speed Signaling Current, TPB+, TPB- Test Conditions 56 load Drivers disabled Driver enabled, speed signaling off* 200 Mbits/s speed signaling enabled 400 Mbits/s speed signaling enabled Symbol VOD VOFF IDIFF ISP ISP Min 172 -- -1.05 -2.53 -8.1 Typ -- -- -- -- -- Max 265 20 1.05 -4.84 -12.4 Unit mV mV mA mA mA
* Limits are defined as the algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- as the algebraic sum of driver currents. Limits are defined as the absolute limit of each of TPB+ and TPB- driver currents.
Table 124. Device Characteristics Parameter Supply Current: D0, 3 Ports Active Cycle Starts on Bus D0, 2 Ports Active Cycle Starts on Bus D0, 1 Port Active Cycle Starts on Bus D1, LPS On, Link Ready, 1 Port Active, PCI Clock Off (or Very Slow) Wake-up is Possible from This State D2, LPS Off, PCI Clock Off (or Slow), Ports Suspended, PHY Core Off, Wake-up is Possible from This State D3Hot, LPS Off, PCI Clock Off (or Slow), Ports Disabled, PHY Core Off, Wake-up is Possible from This State D3Cold, Power is Removed from Chip, No Wake-up is Possible from This State High-level Output Voltage Low-level Output Voltage High-level Input Voltage Low-level Input Voltage Pull-up Current, RESETN Input Test Conditions VDD = 3.3 V Symbol IDD -- -- -- 158 140 122 -- -- -- mA mA mA Min Typ Max Unit
--
86
--
mA
--
<1
--
mA
--
<1
--
mA
-- IOH max, VDD = min IOL min, VDD = max CMOS inputs CMOS inputs VI = 0 V VOH VOL VIH VIL II VDD - 0.4 -- 0.7VDD -- 11
0 -- -- -- -- --
-- -- 0.4 -- 0.2VDD 32
mA V V V V A
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Timing Characteristics
Table 125. Switching Characteristics Symbol -- -- tr tf Parameter Jitter, Transmit Transmit Skew Rise Time, Transmit (TPA/TPB) Fall Time, Transmit (TPA/TPB) Measured TPA, TPB Between TPA and TPB 10% to 90% 90% to 10% Test Conditions -- -- RI = 56 , CI = 10 pF RI = 56 , CI = 10 pF Min -- -- -- -- Typ -- -- -- -- Max 0.15 0.1 1.2 1.2 Unit ns ns ns ns
Table 126. Clock Characteristics Parameter External Clock Source Frequency Symbol f Min 24.5735 Typ 24.5760 Max 24.5785 Unit MHz
ac Characteristics of Serial EEPROM Interface Signals
Table 127. ac Characteristics of Serial EEPROM Interface Signals Symbol fROM_CLK tPW_LOW tPW_HIGH tDATA_VALID Parameter Min -- 4.7 4.0 0.1 4.7 4.0 4.7 0 200 -- -- 4.7 100 Max 100 -- -- 4.5 -- -- -- -- -- 1.0 300 -- -- Units kHz s s s s s s s ns s ns s ns
Frequency of Serial Clock Width of Serial Clock Pulse Low Width of Serial Clock Pulse High Time from When Serial Clock Transitions Low Until EEPROM Returns Valid Data Time I2C Bus Must be Idle Before a New Transaction Can be tFREE Started tHOLD_START FW323 Hold Time for a Valid Start Condition tSETUP_START FW323 Setup Time for a Valid Start Condition tHOLD_DATA Data Out Hold Time for the FW323 tSETUP_DATA Data Out Setup Time for the FW323 Rise Time for Serial Clock and Data Out from the FW323 tRISE_TIME tFALL_TIME Fall Time for Serial Clock and Data Out from the FW323 tSETUP_STOP FW323 Setup Time for a Valid Stop Condition tHOLD_EEPROM Data Out Hold Time for EEPROM
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ac Characteristics (continued)
tPW_LOW tPW_HIGH tFALL_TIME ROM_CLK tSETUP_START ROM_AD IN tDATA_VALID ROM_AD OUT ROM_CLK: serial clock, ROM_AD: serial data I/O
1313 (F) R.02
tRISE_TIME tPW_LOW tHOLD_START tHOLD_DATA tSETUP_STOP tSETUP_DATA
tHOLD_EEPROM
tFREE
Figure 5. Bus Timing
ROM_CLK
ROM_AD
8TH BIT WORD n
ACK tWR(1) STOP START
ROM_CLK: serial clock, ROM_AD: serial data I/O
1314 (F) R.02
Figure 6. Write Cycle Timing
ROM_AD
ROM_CLK STABLE CHANGE ROM_CLK: serial clock, ROM_AD: serial data I/O
1310 (F) R.02
STABLE
Figure 7. Data Validity
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ac Characteristics (continued)
ROM_AD
ROM_CLK START ROM_CLK: serial clock, ROM_AD: serial data I/O
1311 (F) R.02
STOP
Figure 8. Start and Stop Definition
ROM_CLK
1
8
9
DATA IN
DATA OUT START ROM_CLK: serial clock
1312 (F) R.02
ACK
Figure 9. Output Acknowledge
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Data Sheet, Rev. 2 October 2001
Internal Register Configuration
PHY Core Register Map for Cable Environment
The PHY core register map is shown below in Table 128. Table 128. PHY Core Register Map for the Cable Environment Address Bit 0 00002 00012 00102 00112 01002 01012 01102 01112 10002 LCtrl Watchdog RHB IBR Extended (7) Max_speed Contender ISBR Loop Bit 1 Bit 2 Physical_ID Gap_count Contents Bit 3 Bit 4 Bit 5 Bit 6 R Bit 7 PS
XXXXX XXXXX
Jitter Pwr_fail Timeout
Total_ports Delay Pwr_class Port_event Enab_accel Enab_multi
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX Page_select Port_select XXXXX
Register 0 Page_select
11112
Register 7 Page_select
REQUIRED
XXXXX
RESERVED
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Internal Register Configuration (continued)
PHY Core Register Fields for Cable Environment
Table 129. PHY Core Register Fields for Cable Environment Field Physical_ID Size Type 6 R Power Reset Value 000000 Description The address of this node is determined during self-identification. A value of 63 indicates a malconfigured bus; the link will not transmit any packets. When set to one, indicates that this node is the root. Cable power active. Root hold-off bit. When set to one, the force_root variable is TRUE, which instructs the PHY core to attempt to become the root during the next tree identify process. Initiate bus reset. When set to one, instructs the PHY core to set ibr TRUE and reset_time to RESET_TIME. These values in turn cause the PHY core to initiate a bus reset without arbitration; the reset signal is asserted for 166 s. This bit is self-clearing. Used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. See Section 4.3.6 of IEEE Standard 1394-1995 for the encoding of this field. This field has a constant value of seven, which indicates the extended PHY core register map. The number of ports implemented by this PHY core. This count reflects the number. Indicates the speed(s) this PHY core supports: 0002 = 0012 = 0102 = 0112 = 1002 =
R PS RHB
1 1 1
R R RW
0 -- 0
IBR
1
RW
0
Gap_count
6
RW
3F16
Extended Total_ports Max_speed
3 4 3
R R R
7 3 0102
Delay LCtrl
4 1
R RW
Contender
1
RW
Jitter Pwr_class
3 3
R RW
98.304 Mbits/s. 98.304 and 196.608 Mbits/s. 98.304, 196.608, and 393.216 Mbits/s. 98.304, 196.608, 393.216, and 786.43 Mbits/s. 98.304, 196.608, 393.216, 786.432, and 1,572.864 Mbits/s. 1012 = 98.304, 196.608, 393.216, 786.432, 1,572.864, and 3,145.728 Mbits/s. All other values are reserved for future definition. 0000 Worst-case repeater delay, expressed as 144 + (delay * 20) ns. 1 Link Active. Cleared or set by software to control the value of the L bit transmitted in the node's self-ID packet 0, which will be the logical AND of this bit and LPS active. See description Cleared or set by software to control the value of the C bit transmitted in the self-ID packet. Powerup reset value is set by CONTENDER pin. 000 The difference between the fastest and slowest repeater data delay, expressed as (jitter + 1) * 20 ns. See description Power-Class. Controls the value of the pwr field transmitted in the self-ID packet. See Section 4.3.4.1 of IEEE Standard 1394-1995 for the encoding of this field. PC0, PC1, and PC2 pins set up power reset value.
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Data Sheet, Rev. 2 October 2001
Internal Register Configuration (continued)
Table 129. PHY Core Register Fields for Cable Environment (continued) Field Watchdog ISBR Size Type Power Reset Value 1 1 RW RW 0 0 Description When set to one, the PHY core will set Port_event to one if resume operations commence for any port. Initiate Short (Arbitrated) Bus Reset. A write of one to this bit instructs the PHY core to set ISBR true and reset_time to SHORT_RESET_TIME. These values in turn cause the PHY core to arbitrate and issue a short bus reset. This bit is selfclearing. Loop Detect. A write of one to this bit clears it to zero. Cable Power Failure Detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. Arbitration State Machine Timeout. A write of one to this bit clears it to zero (see MAX_ARB_STATE_TIME). Port Event Detect. The PHY core sets this bit to one if any of connected, bias, disabled, or fault change for a port whose Int_enable bit is one. The PHY core also sets this bit to one if resume operations commence for any port and Watchdog is one. A write of one to this bit clears it to zero. Enable Arbitration Acceleration. When set to one, the PHY core will use the enhancements specified in clause 7.10 of 1394a-2000 specification. PHY core behavior is unspecified if the value of Enab_accel is changed while a bus request is pending. Enable multispeed packet concatenation. When set to one, the link will signal the speed of all packets to the PHY core. Selects which of eight possible PHY core register pages are accessible through the window at PHY core register addresses 10002 through 11112, inclusive. If the page selected by Page_select presents per-port information, this field selects which port's registers are accessible through the window at PHY core register addresses 10002 through 11112, inclusive. Ports are numbered monotonically starting at zero, p0.
Loop Pwr_fail
1 1
RW RW
0 1
Timeout Port_event
1 1
RW RW
0 0
Enab_accel
1
RW
0
Enab_multi Page_select
1 3
RW RW
0 000
Port_select
4
RW
0000
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Register Configuration (continued)
The port status page is used to access configuration and status information for each of the PHY core's ports. The port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY core register at address 01112. The format of the port status page is illustrated by Table 130 below; reserved fields are shown as XXXXX. The meanings of the register fields with the port status page are defined by RSC. Table 130. PHY Core Register Page 0: Port Status Page Address Bit 0 10002 10012 10102 10112 11002 11012 11102 11112 AStat Negotiated_speed Bit 1 Bit 2 BStat Int_enable Contents Bit 3 Bit 4 Child Fault Bit 5 Connected Bit 6 Bias Bit 7 Disabled
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
REQUIRED
RESERVED
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Data Sheet, Rev. 2 October 2001
Internal Register Configuration (continued)
The meaning of the register fields with the port status page are defined by Table 131 below. Table 131. PHY Core Register Port Status Page Fields Field AStat Size Type 2 R Power Reset Value -- Description TPA line state for the port: 002 = invalid. 012 = 1. 102 = 0. 112 = Z. TPB line state for the port (same encoding as AStat). If equal to one, the port is a child; otherwise, a parent. The meaning of this bit is undefined from the time a bus reset is detected until the PHY core transitions to state T1: child handshake during the tree identify process (see Section 4.4.2.2 in IEEE Standard 1394-1995). If equal to one, the port is connected. If equal to one, incoming TPBIAS is detected. If equal to one, the port is disabled. Indicates the maximum speed negotiated between this PHY core port and its immediately connected port; the encoding is the same as for they PHY core register Max_speed field. Enable port event interrupts. When set to one, the PHY core will set Port_event to one if any of connected, bias, disabled, or fault (for this port) change state. Set to one if an error is detected during a suspend or resume operation. A write of one to this bit clears it to zero.
BStat Child
2 1
R R
-- 0
Connected Bias Disabled Negotiated_speed
1 1 1 3
R R RW R
0 0 0 000
Int_enable
1
RW
0
Fault
1
RW
0
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Internal Register Configuration (continued)
The vendor identification page is used to identify the PHY core's vendor and compliance level. The page is selected by writing one to Page_select in the PHY core register at address 01112. The format of the vendor identification page is shown in Table 132; reserved fields are shown as XXXXX. Table 132. PHY Core Register Page 1: Vendor Identification Page Address Bit 0 10002 10012 10102 10112 11002 11012 11102 11112 Product_ID Vendor_ID Bit 1 Bit 2 Contents Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Compliance_level
XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX
REQUIRED
XXXXX
RESERVED
Note: The meaning of the register fields within the vendor identification page are defined by Table 133.
Table 133. PHY Core Register Vendor Identification Page Fields Field Compliance_level Size Type 8 r Description Standard to which the PHY core implementation complies: 0 = not specified 1 = IEEE 1394a-2000 Agere's FW323 compliance level is 1. All other values reserved for future standardization. The company ID or organizationally unique identifier (OUI) of the manufacturer of the PHY core. Agere's vendor ID is 00601D16. This number is obtained from the IEEE registration authority committee (RAC). The most significant byte of Vendor_ID appears at PHY core register location 10102 and the least significant at 11002. The meaning of this number is determined by the company or organization that has been granted Vendor_ID. Agere's FW323 PHY core product ID is 03230416. The most significant byte of Product_ID appears at PHY core register location 11012 and the least significant at 11112.
Vendor_ID
24
r
Product_ID
24
r
Note: The vendor-dependent page provides access to information used in the manufacturing test of the FW323.
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Data Sheet, Rev. 2 October 2001
Outline Diagrams
128-Pin TQFP
Dimensions are in millimeters.
16.00 0.20 14.00 0.20 PIN #1 IDENTIFIER ZONE
128 103
1
102
1.00 REF
0.25 GAGE PLANE SEATING PLANE 20.00 0.20 22.00 0.20 0.45/0.75 DETAIL A
38
65
0.106/0.200
39 64
0.19/0.27 0.08
M
DETAIL A
DETAIL B
1.40 0.05 DETAIL B 1.60 MAX SEATING PLANE 0.08
0.50 TYP
0.05/0.15
5-4427r.2 (F)
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Data Sheet, Rev. 2 October 2001
FW323 05 1394A PCI PHY/Link Open Host Controller Interface
Notes
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Data Sheet, Rev. 2 October 2001
Microsoft and Windows are registered trademarks of Microsoft Corporation. MacOS is a registered trademark of Apple Computer, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
October 2001 DS01-124CMPR-2 (Replaces DS01-124CMPR-1)

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